Research And Design Of Digital Filter In High Precision ΣΔ ADC

ΣΔ ADC consists of analog modulator and digital decimation filter,and is widely used in high-precision occasions such as biomedical electronics.The analog modulator determines the conversion accuracy of the entire ADC.Although the digital filter also affects the accuracy of theΣΔADC,it is more important that it occupies a large area in the entire ADC and determines the area and power consumption of the entire ADC.Therefore,it is necessary to study the implementation technology of the digital filter,and reduce the area and power consumption of the digital filter as much as possible on the premise of meeting the ADC conversion accuracy.Based on the third-order single-bit single-loop feedforward discrete-time modulator,this paper studies,designs and simulates various implementation schemes of the digital decimation filter.Among them,the first three-stage cascade implementation scheme of boosted FIR as compensation filter,adopts a 4-level recursive structure Cascaded Integrator Comb filter to achieve 64 times downsampling,a 58-stage boosted FIR filter to achieve passband compensation and a 72-stage Half Band filter to achieve 2 times downsampling and stop-band suppression.The conversion accuracy of this structure is good and the output effective number of bits is 19.30 bits.However,this implementation scheme consumes many multiplier resources.The second four-stage cascade implementation scheme chooses the Interpolating Second Order Polynomials filter as compensation filter.By adjusting the passband compensation factor of the Interpolating Second Order Polynomials filter,different degrees of passband compensation can be achieved.The passband attenuation after compensation is 0.0009762d B.Besides,the interpolation factor of this filter can be set to be the same as the downsampling times of the Cascade Integrator Comb filter to reduce the resource consumption of hardware implementation.Finally,a 12-order Half band filter and a 72-order Half Band filter are cascaded to respectively achieve 2 times downsampling and stop-band suppression.The output effective number of bits of this structure is 19.11 bits.Compared with the scheme of the boosted FIR filter as a compensation filter,the output effective number of bits changes slightly,but the Interpolating Second Order Polynomials filter only has one multiplication operation,and the overall power consumption and area are lower.Then when implementing the RTL code of the scheme of the Interpolating Second Order Polynomials filter as the compensation filter,the structure of the half-band filter is decomposed and the branch is symmetrically,and the filter coefficients are coded as CSD coding style.The functional verification of the RTL code is realized by using MATLAB to process the filtered data.Under the TSMC 130nm process,the filter is logically synthesized,and its timing is constrained with commands such as multicycle path.The final layout is obtained after the completion of formal verification and routing.Finally,the scheme selected in this paper meets the performance requirement of 256 times downsampling,0.01d B passband ripple,120d B stopband attenuation,and the output effective bits are19.11bits.The area of layout is 5.5mm~2.