Design And Implementation Of Network Acceleration System Based On Packet Inspection

With the wide application of the Internet,network traffic has increased significantly,and the network load capacity is meeting great challenges.In order to reduce network load and achieve the purpose of network acceleration,hardware is used to filter packet to reduce the traffic in core network.Therefore,the research on hardware-based network acceleration system is of great significance and value.In this paper,a network acceleration system based on packet detection,which is able to parse packets in high-speed network and filter out user-specified packets from them,is designed and implemented.Firstly,the Internet protocols and some related technologies are introduced,including network acceleration methods and packet inspection methods.Secondly,according to the functional requirements of the network acceleration system,the overall structure,hardware scheme and FPGA scheme of the system are given;Thirdly,the FPGA scheme of packet detection and filtering units are given,every module in the scheme is designed and simulated;Finally,the functions and performance of the system are verified with the network tester.Through system test,the network acceleration system designed in this paper not only supports the correct parsing of network packets and flexible configuration of rules,but also has strong packets filtering performance,which can filter out user-specified packets from large network traffic accurately.Therefore,it reduces the network traffic in subsequent equipment and achieves the purpose of network acceleration.