Low Power FFT Design And Structure Based On Serial Computation Architecture

With the explosive increase of modern information and the continuous improvement of throughput requirements,the hardware implementation of FFT（Fast Fourier Trans-form）needs to take into account both high throughput and low-power design.It has be-come an urgent requirement to be improved in the application scenarios of wireless com-munication and optical networks.In the implementation of FFT with high symmetry in computing structure,while meeting performance requirements,it not only needs high de-gree of parallelism,high hardware efficiency,high system clock,but also urgently needs smaller area overhead and lower power consumption.Therefore,the structure design of FFT with lower complexity is beneficial to achieve higher throughput under the same or lower resource overhead,which will be of great significance to promote high-speed digital signal processing in the future.Bit-serial computing is to refine the operation of data to a single-bit-level pipeline,avoiding the long chain of carry logic in traditional parallel computing,so it has the charac-teristics of low complexity.Using the bit-serial computing architecture,the multiply-add operation in the FFT can be greatly simplified,the parallelism can be improved,and the area efficiency can be increased.In the case of demanding area requirements,a partially parallel structure can be constructed using the storage-based idea to compress the area.If the area constraints are not strict and higher throughput is required,a compromise can be found that uses serial pipelines to shorten the carry chain,and partially uses combinational logic to achieve higher throughput through partially short-chain pipelines.High area ef-ficiency.At the same time,for the 5G NR standard,it is of great research significance to design a low-complexity structure that can satisfy the mixed-base DFT with N=2^a·3^b·5^cpoints.This paper focuses on the low-complexity implementation of serial computing for high-parallel FFT,according to the design of 2^a-point FFT for partially parallel bit-serial computing,the 2^a-point FFT design for multi-bit serial computing,and mixed-radix FFT for serial computing these three aspects:（1）First of all,for the 2^a-point FFT,this part of the paper uses the Cooley-Tukey decomposition algorithm in the algorithm,and uses the high repeatability and symmetry of the fully parallel structure after decomposition to compare the bit-serial bit-level pipeline with the storage-based data processing scheme.Combining,multiplexing the main mod-ules for folding processing to design a partially parallel 2048-point FFT,using only one pre-stage 128-point FFT and 8 post-stage 16-point FFT,the calculated intermediate data is connected through storage scheduling to obtain a partially parallel FFT design.At the same time,the complex multiplier for bit serial calculation and the twiddle factor multipli-cation after folding processing are optimized,and the characteristics of serial calculation are used as much as possible.Compared with the traditional parallel computing FFT of the SDF architecture,the advantages of its area power consumption are analyzed.（2）The second part looks for a compromise between bit serial computing and tra-ditional parallel computing,taking into account the advantages of both,and constructing a serial computing solution with multiple bits as a whole,which is called multi-bit se-rial computing in this paper.The multi-bit serial FFT implementation structure is used to realize the engineering requirements of higher throughput rate.Compared with multiple bit-serial FFT modules working in parallel,it has the advantages of lower complexity and smaller area,which can solve high problems for serial FFT.Throughput and lower area power offer another solution.（3）In the third part,serial calculation is applied to mixed-radix FFT,and the ad-vantage of small-point WFTA（Winograd Fourier Transform Algorithm）in multiplication complexity is only O（N）,combined with the characteristics of serial calculation,we get Better mixed-radix FFT structure design.Through the fusion with mixed base DFT such as base 3 base 5,serial computing can be more flexibly applied to practical digital signal processing engineering need.