Optimal Design Of Filters Based On Digit-serial Computation

The signal processing system is widely used in our life, as an importantpart the digital filter is become the focus of the study. FIR filter has the advantage ofstability, linear phase and design flexibility, so it has been used more frequently.Modern digital signal processing system requires more and more highly on real-timeand flexibility, implementation by software can’t meet the demand for real-time. Inthe hardware method, implementation on FPGA can have the same flexibility as DSP,and real-time access to ASIC, so the FPGA based digital signal processing system isto pay attention to and widely study. We can design the same filter with differentstructure and algorithm but have different hardware occupation and performance.Previous architecture focused on two approaches: bit-serial and bit-parallel. Serialstructure is smaller, but its processing speed is slow; parallel structure ensure that thespeed of the demand, but cause excessive consumption of the hardware, while thechip resources are limited. digit-serial architecture can offer the best trade-off betweenspeed and resource utilization, can improve the implementation efficiency.Firstly, we design the digit-serial structure of adders and multipliers, which arethe basic module of the filter. Compare with corresponding serial and parallelstructure the result indicate that the digit-serial structure can be more efficient. Webuild performance models and hardcores, the later design can be used directly.Secondly, discussed the structure and linear phase of FIR filter, then design itsdigit-serial structure. The performance comparison show that the combined efficiencyof digit-serial structure is better than serial and parallel structure. So the digit-serialarchitecture is effective. Also we added pipeline in the design in order to improve thethroughput of the system.CSD coding can simplified the complexity of multiplier, so the filter can be usedin high speed applications such as video conversion system. This paper design aseven-tap CSD FIR filter with digit-serial architecture, also with serial and DAapproaches. The digit-serial CSD FIR is23%and49%faster than its serial and DAstructures, respectively. And it has11%and32%smaller area-time product than serialand DA filters, respectively. The result show that the digit-serial structure can still effective in the CSD coding FIR filter.