UIS Robustness Study Of SiC MOSFET And GaN HEMT

Compared with Silicon（Si）,Silicon Carbide（SiC）and Gallium Nitride（Ga N）have wider band gap,higher critical breakdown electric field,faster saturation carrier drift speed.They are very suitable for the manufacture of high frequency,high temperature,high power,high energy efficiency,and miniaturization power devices,such as SiC Metal-Oxide-Semiconductor Field-Effect Transistor（MOSFET）and Ga N High Electron Mobility Transistor（HEMT）.Wide-bandgap power devices have broad application prospects in electric vehicles,rail transit traction,and smart grids.Compared with Si-based devices of the same withstand voltage level,SiC MOSFET and Ga N HEMT have smaller chip area,faster turn-off speed,and higher current density,which resulting in more extreme electrical and thermal stress in Unclamped Inductive Switching（UIS）state.Therefore,the UIS robustness of SiC MOSFET and Ga N HEMT faces more severe challenges.Accordingly,facing the urgent demand for high UIS robustness SiC MOSFETs and Ga N HEMTs in high-efficiency and high power density power electronic devices,thesis explores the UIS robustness and failure mechanism of the two devices through experimental testing,simulation,failure analysis and other scientific methods.Research as follows:1.Design and build a UIS robustness test platform suitable for planar SiC MOSFET and p-Ga N HEMT devices,and evaluate the UIS robustness and key criteria of the two devices.SiC MOSFET has an avalanche during UIS,and the three terminals are shortcircuited after failure;p-Ga N HEMT has LC resonance during UIS,and drain-source is short-circuited after failure.The finite element analysis Sentaurus TCAD was used to analyze the electric and heat distribution inside the device during UIS process.The results showed that the temperature of SiC MOSFET increased significantly during the avalanche process,and the failure was closely related to heat accumulation,while the failure of p-Ga N HEMT was closely related to the peak value of the internal electric field.The temperature is not the main factor.2.The chip-level failure analysis of two UIS failure devices was carried out,the failure points and damage characteristics of the devices were clarified,and the corresponding UIS failure mechanism was revealed.The results show that the failure point of the planar SiC MOSFET is located in the surface source metal,and the damage of metal melting occurs.The failure mechanism is that the avalanche voltage and current cause the temperature to increase sharply beyond the melting point of the metal,causing the source metal aluminum to melt and penetrate into the device;p-Ga N HEMT;The failure point is located in the drain-source interconnect metal layer on the drain pad,and the breakdown of the isolation passivation layer between the drain and the source occurs.The failure mechanism is that the high electric field that the device is subjected to during the UIS process makes the isolation between the drain-source interconnect metal layers passivate.The metallization layer is broken down,and the metal layer of the drain-source interconnection is short-circuited,resulting in a short-circuit between the drain and source of the device.This research provides an important theoretical basis and scientific guidance for the subsequent UIS robustness reinforcement of the two devices.