Design And Implementation Of CS Algorithm High Speed Transpose Module In FPGA

Synthetic aperture radar(SAR)plays a huge role in remote sensing technology mapping,military reconnaissance,national economic construction and other fields due to its all-day,all-weather characteristics and high imaging resolution.DSP and DSP plus FPGA are the majority of the hardware mapping solutions for SAR real-time imaging systems,and SAR real-time imaging systems implemented only by DSP are often difficult to image at a higher imaging rate with a larger amount of echo data due to the limitations of their own hardware characteristics,while SAR real-time imaging systems implemented by DSP plus FPGA are often better than the former in terms of real-time performance with the same amount of echo data.However,the data interaction between DSP and FPGA increases the system complexity of the SAR real-time imaging system to a certain extent,while the SAR real-time imaging system implemented by FPGA only can ensure high real-time performance while avoiding the high system complexity caused by data interaction in multi-core systems.Therefore,this thesis combines the features of flexible design and parallel computing of FPGA,based on CS algorithm,through the research and analysis of CS algorithm in MATLAB software,and carries out extensive research on the real-time imaging system of CS algorithm based on FPGA,completes the design and implementation of high-speed transposition module of CS algorithm in FPGA,and completes the design and implementation of CS algorithm real-time imaging system based on FPGA in combination with factor generation module.The design and implementation of the realtime imaging system of CS algorithm combined with the factor generation module is completed,which ensures high real-time performance despite the large amount of echo data:1.Designed the implementation scheme of CS algorithm based on FPGA according to the process steps of CS algorithm,optimized the hardware scheme without large loss of imaging quantization index,and improved the feasibility of porting CS algorithm to FPGA.2.The design and implementation of high-speed transpose,FFT,multiplication module and top-level scheduling module are completed and cascaded,and the correctness of each module is verified by logic simulation.3.Under the premise that the system is designed for synchronous timing logic,the static timing analysis results leave a large timing margin for both establishment time and hold time,which avoids the problem of data instability when the system is running under high load for a long time.4.By comparing the simulation results of Modelsim and MATLAB,it is proved that the system can complete the CS algorithm imaging processing of 512×512×32bits echo data in 0.702 ms with almost no loss of imaging quantization index,and according to the theoretical projection the system can complete the CS algorithm imaging processing of8k×8k×32bits echo data in 178 ms.Theoretically,the system can image 8k×8k×32bits of echo data in 178 ms.