ASIC Implementation Of Satellite Positioning Baseband Signal Acquisition FFT Module

Fast Fourier Transform(FFT)is an optimization algorithm of Discrete Fourier Transform(DFT).FFT reduces the computational complexity of DFT,and this optimization effect becomes more apparent when the number of calculated points increases gradually.The general FFT module is usually based on the IP core inside the FPGA.This type of FFT module has a fixed range for the number of points that can be calculated and the data width,and its input ports and output ports are fixed.This often leads to the waste of internal configuration resources and the problem about redundant port.The IP core is equivalent to a black box for the user,which limits the customized use of the FFT algorithm.It is a low-power module for satellite positioning baseband signal acquisition,so it is necessary to reduce the redundant ports of the FFT module as much as possible.At the same time,it is necessary to reduce the hardware resources occupied by the FFT module as much as possible to further achieve the purpose of low power consumption.Based on the above two points,this paper develops the research of ASIC implementation of the satellite positioning baseband signal acquisition FFT module.The design of this paper is mainly divided into four parts:1)Verilog HDL code design of FFT algorithm;2)Standard cell library design based on UMC55nm process;3)SRAM design based on UMC55nm process;4)Physical realization of FFT operation module and a full layout implementation of the 2048-point FFT.Firstly,according to the data processing requirements of the satellite positioning baseband signal acquisition module,the FFT processing module with corresponding points is customized for it.According to the accuracy requirements of satellite positioning,set the input data width reasonably.Define the input ports and output ports of the FFT module according to the requirements of the front-end code and minimize the port settings to avoid wasting resources.Then based on the UMC55nm process,design the standard cell library.The standard cell library contains basic combinatorial logic gates,such as AND,NOR;sequential logic gate,such as DFF;drive gates,such as INV,BUFFER;physical filling gate,such as FILLER.In this design.,SRAM is mainly used to store intermediate calculation data and final calculation results,and it is mainly composed of memory cells and peripheral circuits.The storage unit adopts a 6-tube structure,and the peripheral circuits mainly include row decoder,column decoder,data writing circuit,and data reading circuit.Finally,through the digital back-end design,the FFT operation module is mapped to the standard cell library,and the circuit file of the layout level is generated.Then realize the interconnection of FFT module and SRAM in Virtuoso to form a complete design.The FFT operation module designed in this paper and the front-end satellite positioning code are jointly debugged,and the correct satellite solution data can be obtained.And the FFT module designed in this paper significantly reduces the occupancy of logic resources.The back-end physical implementation process ensures the reliability of the layout file and the consistency with the transistor-level circuit diagram through DRC and LVS.This design implements a customized FFT module,reduces hardware resource occupation,reduces power consumption,and has certain application value.