Design And Implementation Of The Master Coprocessor In Airborne Data Acquisition System Based On EtherCAT

With the rapid development of large aircrafts,the requirement of manifold,abundant and real-time in airborne data acquisition is increasing,while the traditional PCM system,with the problem of clumsy framing,low speed transporting and high costs operating,can not meet it any longer.Therefore,EtherCAT,an efficient industrial Ethernet protocol operating at the data rate of 100Mbps and the time synchronization accuracy of 1μs,is introduced into the data acquisition system in this paper,and the scheme of combining EtherCAT with the airborne applications is the emphasis of research.Based on the research project of the laboratory named "Design and implementation of airborne data acquisition system based on real-time Ethernet",this paper mainly focuses on the hardware design of the master and the FPGA design of the coprocessor.Firstly,the status and the network trend of airborne test are described briefly and the advantage and the necessity of EtherCAT introduction is analyzed.In the second part,after illustrating the EtherCAT protocol,the hardware design of the system is discussed in detail,including the design of functional block diagram and circuits.The master is composed of two types of PCB boards,which are the main board with a FPGA and the interface board with all the external interfaces.Finally,the FPGA implementation of the master coprocessor is developed.The simulation with Modelsim and the verification on the PCB show that all of the desired research targets is achieved.