Design Of Delay Line TDC In Digital Controlled DC-DC Converter Circuit

With the rapid development of science and technology and the continuous upgrading of electronic products,the design goals of electronic chips are getting closer and closer to people’s lives.With the continuous complexity of electronic product applications,digital power chips have become a hot technology research and development direction.Compared with the traditional analog circuit-controlled power management chip,the digital power chip has the advantages of easy integration,diversified configuration and flexible application.With the advancement of semiconductor process technology,analog power control is more susceptible to noise,internal device matching and other issues.The digital power supply is more process compatible and suppressable,and at the same time,there are new requirements for the area,power consumption and speed of the ADC in the digital power supply.As the CMOS process has entered the deep sub-micron level,the resolution of the voltage domain has been strongly surpassed by the edge resolution of the time signal.Compared with the traditional voltage domain ADC,the time domain ADC can further improve the performance with the shrinking of the process size and the reduction of the power supply voltage.Especially considering the system power consumption and chip area expenditure,the time domain ADC has unquestionable advantages,so it is imperative to further study the time domain quantization ADC in the digital power control chip.In the thesis,a 6-bits 2MS/s delay line TDC is implemented based on the GMSC 0.18μm standard CMOS process,and a switched capacitor sampling circuit with gain multiplication and offset cancellation technology is proposed.At the same time,a method to eliminate the bias voltage that brings quantization error in the delay unit is proposed.The main research and work results of this thesis are as follows:1.By controlling the timing in the switched capacitor sampling and holding circuit,its gain is doubled,which reduces the requirement for the bandwidth of the sampling circuit equivalently.At the same time,by optimizing and improving the traditional sampling capacitor network,the mismatch voltage in the circuit is eliminated,and the linearity of the sampling circuit is improved.The simulation results show that the offset cancellation function works normally,achieves a signal-to-noise ratio of 53.6dB and an effective number of bits of 8.6bits,ensuring that the accuracy of the sampled signal obtained by the TDC meets the design requirements.2.Based on GMSC 0.18μm process,a 6-bits 2MS/s delay line TDC is designed.In the thesis,the non-ideal factors in the TDC are analyzed and explained in detail.Simulation and analysis of the design factors affecting the linearity of the delay adjustment circuit and the quantization amplitude of the delay line in the delay line TDC are carried out.Compared with the traditional structure,the linearity of the time-to-digital converter(VTC,Time-to-digital converter)is further improved by calibrating the error caused by the bias voltage in the delay unit.At the same time,the design of the peripheral bias circuit is completed,and its function and performance are simulated.3.Completed the overall circuit design and layout design,and carried out postsimulation of the overall delay line TDC circuit to obtain various performance indicators.The simulation results show that the core chip area of the delay line TDC is about 0.42mm2.Under the condition of 3V power supply and 2MS/s sampling,the SNR of the delay line TDC reaches 37.68dB,the effective number of bits reaches 5.68bits,and the power consumption is 1.6mW.The range of static index INL is±0.2LSB,and the range of DNL is-0.1LSB～0.2LSB.Compared with the uncalibrated delay line,the TDC effective number of bits is increased by 6%,and the accuracy performance of the TDC is improved.