Research Of Two-step Time-to-digital Converter For Ultrasonic Flowmeter

A Time-to-Digital Converter(TDC)with large range and high precision is designed and implemented for ultrasonic flowmeter and other application scenarios in this thesis.Multiplying Delay-Locked Loop(MDLL)and pulse stretching circuit are used to reach the millisecond scale and picosecond level of accuracy.In traditional TDC design,resolution and range are mutually restricted.In this thesis,an MDLL multiply the low reference clock frequency,which produces the clock for the subsequent circuit and is also used for the coarse quantization.The residual time error is further amplified by a pulse stretching circuit and then fine digitized.Through two-step quantization,this TDC achieves both high resolution and a wide dynamic range.MDLL uses a low-power charge pump structure and a voltage controlled delay line that can be switched to a voltage controlled oscillator to periodically eliminate jitter accumulation while doubling the frequency.An anti-error lock circuit is also added to avoid MDLL locking at the wrong frequency.The pulse stretching circuit widens the pulse according to the difference of discharge time between different capacitors and different currents.A hysteresis comparator is used to compare voltages across different capacitors to avoid false reversals.In this thesis,a low-cost calibration method is designed to calibrate the pulse stretching ratio.The calibration mode requires no additional input signal other than the enable signal,and the calibration result is read as normal operation.Except the pulse stretching circuit,other circuits do not need to be calibrated.With low-cost calibration,TDC works stably in different environments.According to the traditional circular TDC design,the finalization should record the state of the circuit at both the beginning and the end.In order to reduce the complexity of timing sequence and the number of output bits,the TDC designed in this thesis properly processes the start signal of fine quantization,so that TDC does not need to record the circuit state at the beginning of fine quantization,and each fine quantization only needs to record the result once.The TDC designed in this thesis was implemented under the HHgrace 0.11μm standard CMOS process and verified by the flowsheet.The area of the TDC core circuit is 0.065mm~2.The test results show that the power consumption of the TDC core circuit is 1.60m W,the range of the TDC is 4255μs,and the resolution is 5.6ps.The DNL and INL of TDC are±3.06ps and±59.7ps respectively.In the range of an MDLL output clock,the accuracy of the TDC is around 70ps.The final test results show that the TDC can accurately quantify the time interval with lower power consumption and input reference clock frequency.