Research On Modeling And Simulation Technology Of Double-fed Wind Power System Based On FPG

With the goal of "double carbon",the development and utilization of new energy sources have been rapidly developed.As one of the major clean energy sources,wind power plays an important role in the energy transition.Among them,doubly-fed wind power system has been widely used in onshore wind power system with the advantages of mature technology and stable operation.However,the traditional off-line simulation can hardly meet the demand of electromagnetic transient simulation of doubly-fed wind power system,and it is extremely important to study the new generation of real-time simulation.As an emerging real-time simulation device,FPGA(Field-Programmable Gate Array)has become an important tool in the field of real-time simulation of power systems by virtue of its many advantages such as high parallelism and memory distribution.Therefore,a multi-rate parallel real-time simulation method based on FPGA-CPU is investigated in this paper to realize real-time simulation of doubly-fed wind power systems efficiently and accurately.Firstly,the entire doubly-fed wind power system was model partitioned to complete the decoupling of the back-to-back converter from the remaining system.The decoupled back-to-back converter is set to run in the FPGA with small steps,while the rest of the system is simulated in the CPU with large steps.To address the problem of errors in data interaction between the segmented asynchronous parallel systems,PWM integration averaging is used to process the small-step data,and based on this,an improved linear interpolation method combined with Newton interpolation is proposed to complete the prediction and compensation of the large-step data.Secondly,the back-to-back converter is modeled using the switching function method,the improved associated discrete circuit model method and the generalized small-step model method,and its structure is optimized based on the time-division multiplexing principle of small-step timing and the fixed delay strategy.The circuit models before and after the optimization of the back-to-back converter structure are built using HDL Coder library components,and the FPGA code is developed and verified on this basis.Finally,an FPGA-CPU multi-rate parallel co-simulation platform is built using the Ethernet UDP protocol as the communication means,and experiments are conducted based on this platform.The back-to-back converter models under the switching function method and the small step model method are run in the FPGA with small steps of 200 ns and 1 μs respectively,while the remaining part of the system is simulated in the CPU with a large step of 50 μs,i.e.,the FPGA-CPU multi-rate parallel co-simulation of200ns/50μs and 1μs /50μs is realized.Based on this real-time simulation platform,several simulation scenarios are set up and the simulation results of each scenario are compared and analyzed to verify the accuracy and real-time of the FPGA-CPU multirate parallel co-simulation method in this paper.