Research On Real-time Simulation Modeling And Resource Optimization Methods Of Multi-switch Power Electronic Converter Based On FPGA

Field Programmable Gate Array（FPGA）has the advantages of powerful parallel computing capability and up to nanosecond simulation step,and it has quickly become the first choice for real-time simulators of power electronic systems.It has become a trend to decompose variable topology of complex power electronic systems into smaller scale subsystems for modeling.With the increase of circuit scale,a reasonable selection of limited bit-length is an effective method to solve the scale problem of FPGA-based power electronic converter real-time simulation.Although the relationship between state variable bit-length and model accuracy has been studied at present,the quantitative selection of coefficient bit-length is ignored,and a detailed improvement solution needs to be proposed.This thesis focuses on detailed research on the problem that the scale of FPGA-based power electronic converter real-time simulation is mainly limited by FPGA hardware resources.The specific work contents completed are as follows:（1）The basic principle of combining the no-latency decoupling method with ADC（Associated Discrete Circuit）modeling and R_ON/R_OFF modeling is specifically analyzed,and the system is decoupled into multiple independent subsystems for parallel computing.The applications in the T-type（T-type Neutral Point Clamped,TNPC）three-level converter and high-speed train traction electric drive system with the neutral point clamped（Neutral Point Clamped,NPC）inverter as the traction inverter prove the accuracy and universality of the decoupling model.（2）The quantitative selection method of bit-length based on signal-noise ratio is improved.By introducing concepts of quantization error and signal-noise ratio,the necessity of selecting coefficient bit-length and the importance of reducing hardware resources are demonstrated,and the quantitative relationship among coefficient bit-length,state variable bit-length and the signal-noise ratio is deduced in detail.Also the specific bit-length selection order and formula are given,which provide a theoretical basis for the subsequent application of FPGA resource optimization method.（3）Aiming at the two decoupling modeling methods of ADC and R_ON/R_OFF,an improved FPGA resource optimization strategy based on the decoupling model is proposed.A fast automatic generator,where any power electronic decoupling system can automatically generate the optimal coefficient bit-length and variable bit-length of each subsystem,is proposed for the complex quantitative calculation process of signal-noise ratio.Also the bit-length selection principle of each subsystem is presented.The offline simulation results prove the correctness and efficiency of the proposed improved FPGA resource optimization method and fast automatic generator.（4）The structure and development process of the FPGA-based real-time simulation system used in this thesis are specifically introduced,and the Hardware in the Loop（HIL）real-time simulation experiments of the VHLS-based multi-switch TNPC converter and NPC traction inverter are completed respectively.The comparison results of HIL output waveforms and FPGA resource consumption fully verify the feasibility and effectiveness of the decoupling modeling method and the improved FPGA resource optimization strategy,which have great engineering application significance.