Frequency Domain Filtering IP Design And Verification

When the infrared imaging detection system on high-speed aircraft collects images,the quality of the images received by the system is greatly reduced due to the existence of aerothermal radiation effects,which has negative effects on subsequent image processing tasks such as target detection.This thesis aims to develop the image processing acceleration module in the intelligent image co-processor chip.According to the characteristics of aerothermal radiation degraded images,based on the analysis of various correction algorithms and their hardware implementation schemes,a single-precision floating-point frequency domain filtering IP is designed to accelerate the recovery of aerothermal radiation degraded images,which finally meets the requirements of the project’s data processing speed and image restoration effect.The single-precision floating-point frequency domain filtering IP supports Butterworth filtering and threshold filtering operations,and the filtering parameters can be configured to meet the needs of noise image restoration in different scenarios.In view of the requirement that the hardware circuit design must minimize the resource overhead,this thesis analyzes the data path of Butterworth filtering and threshold filtering,and designs the hardware resource sharing of related floating-point operation units that are used by the two to reduce the circuit area.Aiming at the problem that the data path operation delay is too large to reach the preset operating frequency,multi-stage pipeline design is used to solve the problem based on the analysis of the timing sequence of the critical path using the synthesis software Design Compiler.Aiming at the problem that the output delay of the floating-point division and addition unit is too large to be solved by multi-stage pipeline design,multiple parallel design are adopted to work by instantiating multiple identical arithmetic units,which are set to multi-cycle paths,so that the circuit can reach the required data pass rate.Following the above scheme,this thesis completes the circuit design,functional verification,synthesis and timing simulation of the single-precision floating-point frequency-domain filtering IP based on the SMIC55nm process.The circuit after layout and routing has passed the timing simulation verification under 12 corners required by SMIC,and the maximum operating frequency is 320MHz.The data pass rate of IP is3.12*10~8Pixel/s.It takes about 3.28ms to process a frame of 1024*1024 size image,and the processing speed reaches 297fps.