Research On Underwater Timing And Time-keeping Technology And Implementation Of FPGA

At present,countries are gradually carrying out the construction of underwater positioning and navigation timing(PNT)systems and related technology research,in order to provide underwater users with all-sea,practical,effective,secure and reliable PNT services.As a key technology in the underwater PNT system,high precision timing and timekeeping technology directly affects the service capability of the underwater PNT system.The use of satellite timing combined with a high-performance local timekeeping clock to design a high-precision and highstability timekeeping module is a practical solution to achieve high-precision time frequency.At the same time,in recent years,chip atomic clocks are more and more important to all countries Chip-level atomic clocks(CSAC)have the characteristics of miniaturization,low consumption,high accuracy,has a broad application prospect,very cooperative for the local timekeeping module clock.The main work of this paper is to combine Zynq and CSAC to design a timekeeping module for providing high-precision time frequency,providing external second pulse signal and also providing microsecond calendar time information.This paper uses a combination of the multiphase clock sampling method(MPCS)and electronic counting method to design a time digital converter(TDC),and the minimum accuracy of the designed TDC is 0.3125 ns.Firstly,the clock difference(phase difference)between the second pulse(1PPS)of the GPS module and the second pulse of the CSAC is measured by TDC to obtain the original clock difference data.The median method is used to coarse difference rejection of the original clock difference data.Then the data after coarse difference rejection is filtered by an unbiased FIR filter,and the clock difference and frequency deviation of the CSAC are estimated.Finally,the adjustment amount of CSAC is obtained from the estimated clock difference and frequency deviation of CSAC,and the CSAC is tamed by an improved ping-pong algorithm.In this paper,we refer to the method of constructing frequency deviation data using overlapping Allan variance and overlapping Hadamard variance,and construct a set of average frequency deviation data over large-scale time interval,using this set of data as a reference.The estimation effect of clock difference and the estimation effect of frequency deviation of least squares,Kalman filtering algorithm and unbiased FIR filtering algorithm are analyzed and compared.This paper adopts the ping-pong algorithm for taming chip-level atomic clocks,and makes improvements to the formula for calculating the frequency adjustment amount in the ping-pong algorithm.Two improvements are proposed,and a taming process for chip-level atomic clocks is proposed,in which the taming period can be dynamically adjusted during the taming process of chip-level atomic clocks.When using the second pulse output from a GPS module with a timing accuracy of 20 ns as the taming source,the taming time takes about 1 hour to tame the chip-level atomic clock.The clock difference at the completion of the chip-level atomic clock taming fluctuates between-12 ns to 12 ns.The clock difference fluctuates between-25 ns to 15 ns and within 30 minutes after the chip-level atomic clock is tamed.The clock offset of the tamed chip-level atomic clock after8 days is 18.814μs.The predicted clock offset of the tamed chip-scale atomic clock after 1month is 297.157μs.Meet the target of one month clock difference offset not more than 1ms.