Research Of Low-Power Phase-Locked Loop For In-Car Intelligent Devices

With the rapid development of global intelligent applications,the In-car smart devices of alternative fuel vehicles(such as security systems,entertainment systems,sensor systems,etc.)are gradually realizing the functions of smartphones,and leading another huge market and research hotspot of global intelligent terminals.As one of the indispensable modules of wireless transceivers in vehicle intelligent devices,the performance and power consumption of phase-locked loop(PLL)block play important roles in the integrated circuit.Therefore,the study of low power and high performance PLL has significant meaning,in pressing ahead the development and application of intelligent systems for alternative fuel vehicles.This thesis addresses the research and realization of a 2.4GHz low power PLL integration circuit for In-car smart devices on40 nm CMOS process.The main work and achievements of this dissertation are as follows:First of all,the structure and principle of PLL are analyzed,the phase noise models are established by Matlab tools,and the the system-level behavior models of Simulink is designed and verified.Next,the design and simulation of the sub-circuit of PLL is carried out.In the design of the voltage-controlled oscillators(VCO),the low power consumption and the low phase noise of VCO are realized by using capacitor arrays and complementary structure with current multiplexing.In the design of the charge pump,a programmable current-steering charge pump and high-gain operational transconductance amplifier are designed,which achieve a lower static current mismatch ratio through repressing the current sharing effect and increasing the output impedance of the charge pump current source.In the design of the divider,a noval TSPC divider unit and a cascade programmable divider with a wider frequency dividing range were implemented to reduces the design trade-off between dividing range and output frequenc,and achieves a broadened dividing ratio and optimized current power consumption.In addition,considering the loop bandwidth are greatly impacted by VCO’s frequency tuning gain and PVT conditions,this thesis brings forward a loop bandwidth calibration technology to overcome the variation from process corner.The impact of passive devices on the loop bandwidth is reduced by using a charge pump reference current source that is inversely related to the zero resistance of the loop filter,reducing the effect of the loop filter’s process deviations on loop bandwidth,and using the calibration loop to calculate the frequency tuning gain of different bands,then adjusting the charge pump current to keep the loop bandwidth relatively constant which ensures the stability of the system.Finally,the layout design and post-simulation are performed for the designed phase-locked loop circuit.Based on the 40 nm CMOS process platform,the layout area is 416.118um*336.700um(excluding the digital calibration block).And the post-simulation results show that,when the power supply voltage is 1V,the reference frequency of the phase-locked loop is 32 MHz,the lock time is 32 us,the phase noise is-112.67 d Bc/Hz@1MHz,the output frequency range is 2.193GHz-2.576 GHz,and the overall current consumption is 1.949 m A.The circuit performance of this thesis can reach the expected design specifications and has the advantage in low power consumption.