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Design Of Low Voltage DC Carrier System And Slave Transceiver Chip

Posted on:2024-02-14Degree:MasterType:Thesis
Country:ChinaCandidate:W B DuanFull Text:PDF
GTID:2542307067493644Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
New DC-friendly environments are bringing about the emergence of DC power and DC gadgets.Signal and power co-channeling on the same cable is made possible by low-voltage DC carrier technology,which is extensively used in smart home,Internet of Things,and industrial automation because it reduces wiring complexity and costs significantly.This work designs a low-voltage DC carrier system and specifically develops a slave transceiver chip.The following is the paper’s primary contribution:(1)This paper designs a low-voltage DC carrier system based on three DC-powered bus technologies,and uses downlink voltage modulation and uplink current modulation to achieve mutual communication between master and slave stations.A microprocessor(MCU),a level conversion circuit,and a current sensing circuit comprise the master station.The level translation circuit converts logic signals into power line voltage variations,and the current detection circuit converts power line pulse currents into logic signals.(2)The slave transceiver chip includes a power supply module,a transceiver module,and an auxiliary module.The power supply module supplies power to the chip’s internal circuitry and external MCU and load.The receiver module converts the voltage signal transmitted from the master to the power line into a logic signal;the transmitter module converts the slave logic signal into a power line pulse current;and the auxiliary module protects and configures the chip.Based on the UMC180BCD process,the circuit design,pre-simulation verification,layout drawing,and post-simulation verification of the slave transceiver chip are completed.The delay time of the receiver module is 51.1 ns,the delay time of the transmitter module is 116.8 ns,and the accuracy of the LDO output voltage is within 3%of the pre-simulation results.In the post-simulation results,the delay time of the receiver module is 68.7 ns,and the delay time of the transmitter module is 166.45 ns,both of which meet the design requirements.The chip’s total size is 1.89 mm~2.The slave chip designed in this paper has been tapeout and the test results show that the power supply module can output 3.3V and adjustable 5-24V at an input voltage of 10-30V with a maximum load current of 10m A.The receiver module can convert the power line voltage signal normally at a transmission frequency of 100k Hz with a delay time of 286ns.The overall quiescent current of the chip is only 144.89μA.Based on the test results,the relevant circuit was optimized to further improve the circuit performance.
Keywords/Search Tags:Low-voltage DC carrier system, Power supply bus, Slave transceiver chip, Chip design, Chip test
PDF Full Text Request
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