Research On The BP Decoding Algorithm Of Polar Codes In FPGA

Polar codes,firstly proposed by Arikan in 2009,are based on channel polarization.Polar codes are the first channel coding method that can be rigorously proven to reach the Shannon limit.There are two mainstream decoding schemes for polar codes,the first is the Successive Cancellation（SC）decoding algorithm,which is based on serial computation,has low decoding complexity but high decoding latency.The second is the Belief Propagation（BP）decoding algorithm based on parallel computation,which has low decoding latency and is well suited for hardware implementation.In this thesis,the original BP decoding algorithm and the BP decoding algorithm with the early termination iteration mechanism are implemented on the FPGA.It is found that the traditional hardware implementation of the BP decoding algorithm has the problems of low utilization of Basic Computational Block（BCB）resources and high consumption of logic unit resources.Therefore,a hardware implementation scheme based on module reuse is given for the above problems.The main work of the thesis is as follows:1)The hardware implementation is carried out,based on the in-depth understanding of the principle of the BP decoding algorithm of polar codes.Two major factors,including decoding latency and functional unit consumption,are considered to design each module.The hardware design architecture is divided into the following aspects:quantization scheme,top-level architecture,control output module Switch1,control input module Switch2,hard judgment module,and basic calculation unit module.After the hardware design is completed,the decoding results which are simulated using Modelsim,are compared with the decoding results simulated by Visual Studio,to verify the correctness of the implementation scheme and to complete the timing analysis.2)To address the problem of high decoding latency in the original hardware implementation scheme,an early termination iteration module is added.After each iteration,the code word is judged and verified using the generation matrix.Finally,the performance of the two hardware design schemes is compared in terms of decoding latency and logic unit resource consumption.The results show that after the early termination iteration module is added,each iteration needs an additional clock to perform the verdict and checksum,so the average iteration latency increases by 1.In addition,additional registers are needed to store the generation matrix,and additional logic computation units are needed to perform the checksum operation,so the resource requirements of logic units are increased by 39.1%,but the decoding latency decreases significantly compared with the original implementation.3)Due to the differences between each layer of the decoding structure,the original implementation requires separate modules for each layer of the structure,resulting in a large resource requirement for the logic unit.The BCBs of one layer are computed in each clock,while other layers are idle,resulting in low resource utilization of the BCBs.In this thesis,the module reuse scheme is given by unifying the decoding structure of each layer in the factor graph.The results show that the iteration latency of the hardware implementation based on module reuse is doubled compared with the original BP decoding algorithm implementation,but the logical unit resource requirement is significantly reduced to 41.2%of that of the traditional implementation,and the BCB resource utilization is increased from1/log_N to ₁/2.