Research And Design Of Sub-GHz CMOS Transmitter Circuit

In recent years,long-distance communication,regarded as a realistic basis of the global village,has made people communicate without geographical restrictions and became a convenient new pattern in online communication.And consumers have always set their high expectations on the transceiver system which the long-distance communication relies on,including the miniaturization required by the convenience of a carry,the low power consumption required by the long endurance,the low cost required by the popularity of the product and so on.These requirements have shown social progress and people’s growing demand for a better life,and consequently pose a challenge to the work of designers.In order to meet the requirements of low cost,miniaturization and low power consumption for future wireless communication system,the research of integrated transmitter which can be configured with multi-standard multi-band/wideband has been paid enough attention.This thesis mainly focuses on the Sub-GHz transmitter system architecture and parameters,and we propose the improvement of circuit structure and the performance optimization for Phase Locking Loop and Power Amplifier modules.The main research work of this thesis is as follows:1.A feedback loop is introduced in the charge pump to reduce the current mismatch caused by the change of the output voltage of the charge pump.The current mirror mismatch caused by the voltage difference between gate and source can be effectively suppressed by feeding the output voltage of charge pump back to the current mirror control voltage through the feedback loop.2.The two-stage Cascode structure of switching transistor in power amplifier is adopted to improve the voltage of power supply while ensuring reliability.The two-stage Cascode structure can improve the power amplifier supply voltage to 3.3V,reduce the bias current,and effectively prevent the breakdown of the 1.2V switch transistor inside the chip.3.The use of multiplexed resonator matching technology,reduces the number of output matching network components.Using the characteristics of LC resonator at different frequencies,the resonator is multiplexed to construct the impedance required for each harmonic,which reduces the production cost.A Sub-GHz transmitter chip is designed based on the SMIC 0.18μm process,and the internal power supply is 1.2V.The independent simulation output frequency of PLL module can reach 315MHz/434 MHz,and the output phase noise is-110.9d Bc@1MHz.The independent simulation output power of the power amplifier circuit reaches 14.94 d Bm,the maximum drain efficiency reaches 53.4%,and the harmonic suppression reaches the requirement of-40 d Bm.The functional verification of the system based on 1527 code shows that the harmonic suppression is less than-40 d Bm,which meets ETSI-EN 300 220 standard.