Design And Implementation Of Low Power Wide Area Network Physical Layer Based On LoRa Modulation

The Internet of Things(IoT)has played an increasingly important role in the era of the Internet of Everything.As one of the emerging technologies of Low Power Wide Area Networks(LPWAN),LoRa(Long Range)is widely used in the field of low traffic,wide coverage,high-density connection such as smart citie,smart transportation,smart logistics,environmental monitoring and so on.Io T nodes need to work for a long time,and it is difficult to replace the battery in some environments,so how to further reduce the complexity and power consumption of LoRa Io T nodes has become a research hotspot.In this context,this paper studies and improves the traditional algorithm of LoRa physical layer and builds a Software Defined Radio(SDR)platform for hardware implementation and link testing by FPGA.The main work of the thesis is as follows:Firstly,an overview of the LoRa physical layer and the principle of its key modulation method FSCM(Frequency Shift Chirp Modulation)are introduced.On this basis,An improved low-complexity transceiver algorithm is proposed.In order to adapt to the minimum sampling rate of the DAC and meet requirements of the subsequent clock design,the transmitter performs 32 times up-sampling and low-pass filtering after framing coding.Then,low-complexity algorithms of frame detection,symbol synchronization and frequency offset estimation are designed,and waveform matching after direct demodulation is used to improve system reliability.Then,based on the improved algorithm,a communication system is built and its performance is simulated.The simulation results show that the algorithm guarantees the system performance of synchronization and bit error rate as a whole.Secondly,the FPGA architecture of low-complexity transmitter is designed.The module of frame control dominates the CRC coding,Gray inverse mapping,reduction set,differential coding,FSCM modulation,upsampling and half-band(Half Band,HB)filtering,which are executed in parallel according to the pipeline to reduce the switching delay between modules and increase the speed of transmitter data processing and system throughput.Among them,the chirp symbol cyclic shift for FSCM modulation is realized by controlling the initial address of the ROM,thereby reducing the complexity and power consumption of the transmitter.Thirdly,the FPGA architecture of low-complexity receiver is designed,then the scheme of hardware implementation and simulation results of key modules are given.The receiver works under the minimum sampling rate clock and is controlled by a state machine as a whole.The specific states include initialization,frame detection,symbol synchronization,CFO(Carrier Frequency Offset)estimation,equivalent channel estimation,and demodulation and decoding.Finally,the RF interconnection test of the physical layer transmitter and receiver is carried out by the SDR platform,and the overall architecture design of the baseband processor(BBP)and the RF communication module AD9361 is introduced.Lastly,the correctness of the designed algorithm,transmitter and receiver are verified according to the test results.