Design And Modeling Of Electric Field Modulation Terminal For Lateral Heterojunction Power MOS

Power semiconductor devices are the core of power electronic systems and power integrated circuits,and their performance affects the utilization of human energy and the development of power integrated circuits.Lateral double-diffused metal-oxide-semiconductor field-effect transistor(LDMOS)is one kind of power devices.Because its electrodes are located on the surface,it is easy to integrate with peripheral circuits and is widely used in high-voltage integrated circuits.The contradictory relationship between breakdown voltage and specific on-resistance limits the performance improvement of LDMOS devices.The development of traditional LDMOS devices is limited by Si materials,in order to further improve the performance of power devices,researchers replace the traditional material Si with SiC.The advantages of wide band gap,high critical breakdown electric field,and high thermal conductivity make SiC materials very suitable for high-voltage power MOS devices.The development of SiC power devices is limited by the poor quality of the gate oxide layer,difficult doping,and difficulty in fabrication of low ohmic contact resistance.The appearance of Si/SiC heterojunction provides a new direction for the design of high-voltage power MOS devices.Si/SiC LDMOS can take advantage of the mature technology of Si material and the characteristics of high-voltage resistance of SiC material;However,Si/SiC LDMOS increases the breakdown voltage,but also brings the problem of increased specific on-resistance.In order to further improve the performance of Si/SiC LDMOS and give full play to the advantages of Si/SiC heterojunction materials,this thesis designs two novel Si/SiC LDMOS devices.The innovative work and achievements of this thesis are as follows:(1)A Si/SiC heterojunction LDMOS with a P-type buried layer is designed.The electrode of the device is fabricated on the Si layer to avoid process problems such as gate oxide layer and ohmic contact of SiC material;P-type buried layer is introduced at the bottom of the device drift region,and the lateral electric field of the device is optimized by electric field modulation technology;The drain region of the device goes deep into the SiC substrate,and the vertical electric field of the device is optimized by the breakdown point transfer technology.The simultaneous optimization of the lateral and vertical electric fields improves the breakdown voltage of the device;The P-type buried layer participates in the depletion of the drift region,which increases the doping concentration of the drift region and reduces the specific on-resistance of the device.The influence of key parameters on device performance was analyzed with the help of simulation software.The research results show that when the drift region length is 20μm,compared with Si/SiC LDMOS device,PBL Si/SiC LDMOS device,the breakdown voltage is increased from 384V to 440V,an increase of 15%,and the specific on-resistance is reduced from 34.6mΩ·cm~2 to 30.4mΩ·cm~2,a 12%reduction.The device power figure of merit increased from4.26MW/cm~2 to 6.37 MW/cm~2,an increase of49.5%.In addition,the drift region of the PBL Si/SiC LDMOS device is mathematically modeled,and the influence of the key parameters of the device on the performance of the device is studied,which provides theoretical guidance for the simulation of the device.(2)A Si/SiC heterojunction LDMOS with accumulation mode is designed,an oxide layer is grown on the surface of the Si/SiC LDMOS drift region and a layer of single crystal silicon is bonded.Different regions of the top layer silicon are doped to form two PN junctions connected to the cathodes.No matter whether the device is turned on or off,a PN junction of the top layer silicon is in a reverse bias state,which avoids the generation of gate leakage current.When the device is conducting forward,an electron accumulation layer will be formed on the surface of the AC Si/SiC LDMOS drift region,and its concentration is much higher than the doping concentration of the drift region.The on-resistance of the device is mainly determined by the electron accumulation layer,which reduces effect of doping concentration versus on-resistance,so the specific on-resistance is greatly reduced;The top layer of silicon has little effect on device breakdown characteristics.The research results show that when the drift region length is 20μm,the breakdown voltage of AC Si/SiC LDMOS device is reduced from 384V to 380V compared with Si/SiC LDMOS,which is 1%lower.The specific on-resistance is reduced from 34.6mΩ·cm~2 to 9.3mΩ·cm~2,a decrease of73%,The device power figure of merit increased from 4.26MW/cm~2to 15.5MW/cm~2,an increase of 264%,and the performance of AC Si/SiC LDMOS devices was greatly improved.In addition,a simple AC Si/SiC LDMOS drift region specific on-resistance and withstand voltage model is also given.