Research On Polar Coded CPM System And FPGA Implementation Of Decoder

Because of high spectrum utilization,high power utilization,and constant envelope characteristics,continuous phase modulation(CPM)has been used in various military and civilian applications.However,in long-distance transmission,which has low signal-to-noise ratios(SNRs)and the Doppler effect,the performance of communication system will degrade,which makes the needs for reliability of system are higher than ever.The researches on serially concatenated continuous phase modulation(SCCPM)show that it can provide high reliability for communication system,therefore the researches on sccpm deserve further investigation.Polar codes became the coding scheme for control channels in 5G enhanced mobile broadband scenarios,because of excellent performances with medium and short code lengths.Based on the advantages of CPM and Polar codes,in this thesis,the system aims to provide a solution for medium and short packet communication under minimum shift keying(MSK)modulation.The main works of this thesis are as follows:(1)The polar coded NR-MSK system is proposed to achieve high spectral efficiency,high power utilization and high reliability in satellite communication.Firstly,the fundamental of CPM is introduced.Then,we presented the Rimoldi decomposition of CPM and two demodulation algorithms.By comparing the two forms of continuous phase encoder(CPE)in Rimoldi decomposition,namely recursive structure and non-recursive structure,we finally choose the non-recursive form of MSK as modulator section in this thesis.The simulations show that,by joint demodulation and decoding iterating,the system can resist the effect of large phase offsets with the phase offset estimation method.(2)The belief propagation(BP)decoding algorithm of polar codes is highly worthy to implementing since its outstanding characteristics of soft input and soft output and high throughput.Based on the hardware platform of Xilinx ZYNQ-7 ZC706 evaluation board(xc7z045ffg900chip),this thesis shows the field programmable gate array(FPGA)implementation of bp decoder supporting any bit rate.The implementation can be configured with different numbers of processing units and meet different requirements for throughput and implementation resources.The final results show that the decoder operating frequency reach at most 220 MHz.With the working frequency of 220 MHz and the decoding iterates of 20 times,the throughput rate can achieve 13.7Mbps.The resource occupancy of(1024,512)BP decoder under different number of processing units is given.