A Coprocessor Design For Accelerating RSA/ECC/SM2 Public Key Cryptographic Algorithms

In the era of the “Everything Interconnected”,the importance of information security has gradually attracted attention.As one of the cryptographic systems,public key cryptography has played a very important part in ensuring information security.RSA,ECC and the SM2 public key cryptography algorithm are currently the most widely used public key cryptography algorithms.However,the principle of public key cryptography is complex and the amount of calculation is large.Traditional embedded processors use software to calculate not only slow,but also vulnerable to attacks and information leakage.Designing a coprocessor dedicated to accelerating public key cryptographic algorithms that can be mounted on an embedded processor has full practical significance at present.At present,there are many different standards for the use of public key cryptographic algorithms in the industry.In order to be compatible with as many standards as possible to achieve a wider range of applications,the coprocessor designed in this paper should support three mainstream public keys:RSA/ECC/SM2 cryptographic algorithm.In this paper,we proposed a coprocessor architecture that is compatible with the acceleration of the RSA/ECC/SM2 public key cryptographic algorithms.When calculating the RSA,it supports operations of 4096 bits and any key length below.When calculating the ECC or SM2,it supports the calculation of 384 bits curves and length below.The algorithm structure of this design is clear,the reusability is good,and the hardware resource overhead is small.In the underlying algorithm,the optimized Montgomery algorithm is used to implement the modular multiplication circuit,and the design of parallel processing and pipeline is used to improve the throughput of the circuit.In the middle-level algorithm,the fast exponentiation algorithm is used to design the modular exponentiation algorithm,and the appropriate coordinate system is selected according to the two calculation domains to implement the point addition and point-double algorithms.In the top-level algorithm,Euler’s theorem is used to implement the modular inverse algorithm under the dual domain,and the L-R scanning method is used to implement the point multiplication algorithm.Finally,other control units inside the coprocessor are designed,and the APB slave interface for connecting the bus is designed on the top layer.In order to verify the functional correctness of the coprocessor,the behavioral simulation and FPGA test of the coprocessor are carried out in this paper.The test results show that the internal logic of the coprocessor is implemented correctly.The coprocessor is implemented on the XC7Z035FFG676-2 device,which consumes a total of 33005 LUTs and 14965 D flipflops.Under the high-speed calculation clock of 100 MHz and the bus clock of 25 MHz,it takes about 744 ms to calculate the 4096-bit RSA modular exponentiation,and the calculation times of 256-bit prime field and 257-bit binary extended field point multiplication are 30 ms and 21.4 ms respectively.The coprocessor designed in this paper has the characteristics of wide algorithm compatibility and small resource overhead,which provides a solution for the application of public key cryptography algorithm in embedded devices.