Design Of RSA Algorithm Hardware Accelerated Coprocessor Based On RISC-V

In recent years,with the rapid development of information technology,people’s lifestyles have undergone tremendous changes compared with the previous ones.For example,applications such as online payment,digital currency,and block chain have provided great convenience to people’s lives.These applications generate a large amount of information data.At the same time,the data transmission volume and transmission frequency are also greatly increased,and the demand for ensuring the security of information data is also increasing.The RSA encryption and decryption algorithm is an asymmetric public key encryption and decryption algorithm.,because of its high security,it is more and more used to ensure the security of information data.Due to the explosive increase in the amount of data,the encryption and decryption time of information is also getting longer and longer,so it is of great significance to accelerate the RSA encryption and decryption algorithm.Compared with software implementation,hardware implementation of RSA encryption and decryption algorithm has a natural speed advantage.After researching and analyzing the RSA algorithm,this paper optimizes and improves the algorithm,and designs and implements the instruction mounted on RISC-V.The coprocessor dedicated to the RSA encryption and decryption algorithm on the Hummingbird E203-V2 So C platform with integrated architecture utilizes the high scalability of the RISC-V instruction set,and customizes multiple instructions to control the coprocessor.Accelerates the RSA encryption and decryption algorithm.The main work of this paper is as follows:(1)The basic principle of RSA encryption and decryption algorithm is analyzed.First of all,for the problem that the number of parameters of the RSA encryption and decryption algorithm is large,by converting two large prime numbers into four smaller prime number s and multiplying them,the key generation time is accelerated.Secondly,the modular exponentiation operation is optimized by combining the R-L scan algorithm and the L-R scan algorithm.Finally,the modular multiplication operation is optimized by the improved Montgomery algorithm combined with the modular multiplication symmetry..(2)The So C platform of Hummingbird E203-V2 is used to complete the design of the entire RSA encryption algorithm acceleration system.First,a number of custom instructions are designed and packaged to call the coprocessor,and then the entire coprocessor architecture is designed.The interface between the coprocessor and the RISC-V soft core is configured,and finally each module of the coprocessor is written by Verilog.(3)The RSA encryption and decryption algorithm test environment is built,and the acceleration of the RSA encryption and decryption algorithm is tested.The test results show that the paper basically realizes the acceleration of the RSA encryption and decryption algorithm.By comparing the time spent by software and hardware to achieve the same function,the consumed instructions are reduced from 16806063 to 6203,and the consumed cycles are reduced from 20362391 to 729865,the encryption and decryption speed is greatly improved,highlighting the speed advantage of the RSA algorithm coprocessor.