The Design Of Clock Circuit And Transport Layer Based On JESD204C Protocol

With the advent of the era of big data,massive amounts of data are generated,transmitted,stored and used,and many of the original engineering application solutions can no longer meet the latest needs.The previous transport protocol has been updated to the JESD204C version on the connection standard between conversion devices and logic devices.Compared with previous versions,JESD204C supports the needs of high-bandwidth applications,increasing the maximum transmission rate of a single channel to 32Gbps,while enhancing link availability and reliability.This paper studies the clock circuit design and transport layer circuit design based on JESD204C protocol,including Ser Des PLL that provides clock for physical layer,device PLL and framing circuit that provides clock for transport layer.The high-speed Ser Des PLL has an output frequency of 12.375GHz and adopts a charge pump structure.The main modules include a voltage-controlled oscillator(VCO),a frequency divider,a frequency and phase detector,a charge pump and a low-pass filter.Among them,VCO adopts complementary cross-coupled LC structure,which has better phase noise while obtaining higher oscillation frequency.The frequency divider adopts the CML structure and the TSPC structure,and uses the CML structure to realize the logic gate function,which optimizes the power consumption while completing the high-speed frequency division function.The output frequency of the device PLL designed in this paper is 3GHz.The VCO adopts the ring oscillator structure and the delay structure of the tailless current source,which increases the output swing.The use of cross-coupled pairs also increases the circuit’s response to large signals.response speed.Under the frame clock frequency of 1GHz,the transport layer circuit uses the data packing format of multi-channel high-density mode without control words,and converts the sampling data of the four converters into sampling word groups according to the protocol,and then uses 6 nibble groups(24bits).It is mapped to 4 channels in units and sent to the post-stage circuit for processing and transmission.In order to enhance the reliability and reusability of the circuit,the whole mapping process is divided into three stages.At the same time,the eight-byte parallel processing method is adopted,which reduces the operating frequency of the digital circuit and simplifies the design.This paper uses 65nm CMOS technology to complete the layout design and post-simulation of12.375GHz Ser Des PLL.The chip area including the pads is 500×550μm~2,and the power consumption is 42.6m W under the 1.2V supply voltage.The post-simulation results show that the phase-locked loop VCO phase noise at 1MHz is-106d Bc/Hz,and the jitter is less than 0.05UI.Based on the 65nm CMOS process,this paper completes the pre-simulation design of the3GHz phase-locked loop circuit.The previous simulation results show that,under the tt process angle,the VCO phase noise of the 3GHz phase-locked loop circuit at 1MHz is-91 d Bc/Hz,the jitter is less than 0.03UI,and the circuit power consumption is 21.5m W.The clock circuit and transport layer circuit designed in this paper to adapt to the JESD204C protocol are of great significance to the current and future localization of high-speed interface circuits in China.