The Design Of Key Circuit For Reciever Based On JESD204C

With the continuous development of modern digital technology,various fields put forward higher and higher requirements for high-speed data transmission,forcing the continuous progress of high-speed digital to analog converter(ADC)and analog-to-digital converter(DAC)technology,and the continuous improvement of converter resolution,sampling rate and bandwidth.With the increase of data throughput per unit time,the traditional communication interface can not meet the needs of high-speed converter.In the past,the mainstream communication interface was CMOS or LVDS parallel communication interface.With the improvement of circuit performance,the traditional high-power multi pin interface circuit is not suitable for high-speed interface circuit.The performance bottleneck limits the development of microelectronic technology.JEDEC Association proposed a high-speed serial interface standard jesd204.Due to the characteristics of low power consumption,few pins and high flexibility of this protocol,In recent years,it has been widely used in various fields.After years of development,the latest version of jesd204 c protocol has a single channel maximum serial rate of 32 gbps,and is more flexible,providing multi-channel transmission,repeatability,deterministic delay and other functional features.This thesis is based on the ASIC implementation of the receiver circuit under jesd204 c protocol.It is designed for the 4-channel 64 b / 66 b and 64 b / 80 B link layer of the receiver.The single channel rate can be up to 24.75 gbps.In this design,the main modules of the link layer circuit at the receiving end include gearbox,head locking module,block synchronization module,descrambling module,crc12 coding module,multi-channel synchronization module and so on.The transmission module realizes 64 b / 66 b and 64 b / 80 B bit width conversion,the head locking module and block synchronization module realize the search and locking of data blocks,the descrambling module and crc12 coding module realize the recovery and error detection of data streams by links,and the synchronization module eliminates the delay between different channels.This thesis is designed in tsmc0 The back-end design of ASIC such as logic synthesis,layout and wiring,clock tree synthesis and static timing analysis are completed under 18 um standard cell library.Finally,the layout is generated and simulated,and the test scheme of the chip is given.The final result works normally at 375 mhz and can meet the requirements of single channel 24.75 Gbps,which is of certain value for the implementation of jesd204 c standard protocol.