Research And Design Of High-Speed Continuous-Time ΣΔ Modulator

The continuous-time ΣΔ modulator adopts oversampling and noise shaping,which reduces the requirements on the accuracy of analog circuits and improves the output accuracy of analog-to-digital converters,and plays an important role in high-speed,medium-high-precision application scenarios.Therefore,it is of great significance to carry out research on it.This paper presents the working principle and structural classification of ΣΔ modulators,as well as the advantages of continuous-time ΣΔ modulators.Under the premise of comprehensive consideration of performance indicators,structural advantages and disadvantages,and design difficulty,the continuous-timeΣΔ modulator is designed using the structure of the third-order four-bit quantized mixed feed-forward feedback.A model of the continuous-time ΣΔ modulator and its non-ideal factors is established in Simulink,and the system design of the continuous-time ΣΔ modulator is completed through simulation and analysis;then the integrator,quantizer,feedback DAC and DWA circuit in the continuous-time ΣΔ modulator are designed.In the active integrator,the operational amplifier uses a two-stage feedforward compensation amplifier to obtain high gain and high bandwidth;a 4-bit Flash quantizer composed of a resistor divider network,preamplifier and comparator is used;the feedback DAC adopts the current steering DAC circuit and adds the switch driving circuit;in addition,a DWA circuit is added to correct the nonlinearity of the DAC,and the PI-Element compensation method is used to solve the excessive loop delay in the modulator.In this paper,the design of the high-speed continuous-time ΣΔ modulator circuit and layout is completed under the 40 nm CMOS process,and the simulation verification is carried out.When the clock frequency is4 GHz and the signal bandwidth is 125 MHz,the SNDR reaches 74.69 d B,the ENOB reaches 12.11 bits and the power consumption is 70.9m W in the pre-modulator simulation;the SNDR reaches 67.79 d B,the ENOB reaches 10.97 bits and the power consumption is 77.4m W in the post-simulation,which meets the index requirements.