Research And Design Of High Energy-Efficiency Audio Continuous Time ∑-Δ Modulator

Today,portable wearable devices have developed rapidly and have broad development prospects,and high-resolution and low-power audio chips,as essential functional modules of portable wearable devices,their demand is also growing.The sigma-delta ADC(Σ-ΔADC),as a typical ADC architecture applied to low-frequency and high-precision ADCs,is widely used in audio chips and has become a key module in audio chips.Therefore,designing a high-efficiency audio Σ-Δ ADC is of great significance for the development of portable wearable devices.The so-called high energy efficiency,that is,to achieve higher resolution analog-to-digital conversion with lower power consumption.The Σ-Δ modulator,as the core module in the Σ-Δ ADC,occupies a large amount of power consumption.Therefore,it is of great significance and practical demand to carry out research on the energy efficiency improvement technology of the Σ-Δ modulator,which is also the focus of this study.In this thesis,a detailed principle analysis,performance index introduction and basic structure analysis of the Σ-Δ modulator are firstly carried out,which provides a strong theoretical support for the modulator to choose a high-efficiency topology structure,and finally determines that the structure used in the design of this thesis is " Continuous-Time Third-Order One-Bit Quantization and Feed-Forward Feedback Hybrid Topologies".In order to improve the accuracy and efficiency of the modulator circuit design,the system design and modeling of the modulator are firstly carried out,and the non-ideal factors of the modulator are analyzed.At the same time,the performance indicators of each module are obtained by modeling the non-ideal factors to guide the subsequent circuit design.In order to improve the energy efficiency of the modulator,this thesis adopts the Negative-R compensation technology to compensate the non-ideal factors of the active RC integrator.The design improves the performance of the modulator by improving the response of the integrator and reducing the thermal noise of the resistor,and also relaxes the specification requirements of the operational amplifier,effectively reducing the power consumption;in addition,by using a feedback DAC with FIR filtering to reduce the large clock jitter noise caused by one-bit quantization,this technology retains the advantages of the multi-bit quantization structure,effectively improving the signal-to-noise ratio of the modulator.At the same time,the circuit achieves simplicity and low power consumption through one-bit quantization,that is,the high energy efficiency of the modulator is realized.Finally,based on the SMIC 0.18 μm CMOS process,the circuit and layout design of the high-efficiency audio continuous-time Σ-Δ modulator are completed,and the postsimulation verification is completed.Finally,a signal-to-noise distortion ratio of 100.7 d B is achieved,the overall power consumption is 161 μW,and the energy-efficiency index Fo M(Figure of merit)is 181.6 d B,reaching a high energy-efficiency level.