Research And Implementation Of Defect Simulation Optimization Algorithm For Analog/Mixed Signal Circuits

For the testability design of analog/mixed-signal circuits,the traditional approach usually requires simulating all defects in the entire circuit.However,with the continuous advancement of integrated circuit design and manufacturing technology,the complexity and scale of integrated circuits continue to increase,resulting in high computational complexity and long simulation time.To address this problem,this paper proposes a method of compressing the number of defects.By reducing the number of defects to be simulated,it is possible to reduce the computational complexity and improve the simulation efficiency,while still maintaining a high defect coverage rate.In addition,this paper also studies the relationship between excellent test points and network node centrality,which can effectively identify critical test points in the circuit during defect detection and improve defect detection efficiency.The main work is as follows:(1)In order to minimize the time required for defect simulation while ensuring a high defect coverage rate,this paper proposes a method for compressing the number of defect sets.By analyzing the structural characteristics of the circuit,compressible defects are classified into four categories: equivalent,redundant,isolated,and invalid.Based on the complex network model abstracted from the circuit structure,four corresponding identification methods are proposed for these four categories of defects.The correctness and practicality of the defect compression identification algorithm are verified on the Benchmark circuit without simulation,using only the netlist information of the circuit.(2)To improve the efficiency of test point selection for testability design and defect detection and reduce the amount of data to be calculated,this paper discusses a test point selection method based on network node centrality.First,all defects in the circuit are simulated to obtain the defect response data of all optional test points,and the centrality of each test point is calculated based on the sensitivity factor.Then,the four centrality indicators of each node in the circuit network model,namely degree centrality,betweenness centrality,closeness centrality,and eigenvector centrality,are calculated.By using two comprehensive ranking methods,weighted Borda count and weighted arithmetic mean,the centrality data is ranked and compared with the circuit key test point data obtained by simulation analysis.The verification results on the gap benchmark circuit show that network node centrality can compress the size of the test point set,thereby reducing testing time and cost.The defect compression method and the test point selection method based on network centrality proposed in this paper can reduce the size of the defect set and test point set while satisfying a certain defect coverage rate,thereby improving testing efficiency and reducing testing costs.