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Research And Implementation Of 3D NAND Flash Testing Technology

Posted on:2024-05-25Degree:MasterType:Thesis
Country:ChinaCandidate:Y K WangFull Text:PDF
GTID:2558307079470354Subject:Electronic information
Abstract/Summary:PDF Full Text Request
Memory,as a medium for storing information,occupies an important position in the integrated circuit industry.With the widespread application of 3D storage technology in NAND Flash production and manufacturing,NAND Flash is developing towards higher storage density,larger storage capacity,and faster data transfer rate,which brings new challenges to the testing of NAND Flash finished products.This project studied the testing method of 3D NAND Flash,developed a testing program for 3D NAND Flash based on ATE,completed the design of high-speed DIB board and transmission line delay compensation,simulated the NAND Flash controller using test vectors,and designed a detailed functional testing and main AC/DC parameter testing program.The main research content of this article includes the following parts:(1)Starting from the basic composition and structure of NAND Flash memory,the physical mechanism of implementing data storage in NAND Flash and the working principles of three basic operations: programming,erasing,and reading were studied.By analyzing the three types of interference faults of NAND Flash programming,erasing,and reading,a NAND Flash fault function model is established.Multiple different memory test graphics are selected for fault detection of NAND Flash chips.(2)Based on the existing V93000 testing platform and board resources,a detailed testing plan has been developed for 3D NAND Flash finished product testing according to the specifications of the chip data manual to be tested.The plan mainly includes analysis of testing system indicators,testing requirements,ATE based testing system structure,and testing development process.(3)Design a high-speed DIB board,use time-domain reflection technology to test the delay time of each transmission line,perform system calibration,and ensure the time synchronization of the driving signal loaded into each input pin of the chip to be tested.Generate test graphics using MTL software programming,simulate NAND Flash controller through test vectors,and complete high-speed signal timing design for NAND Flash command loading,address loading,and data transmission.Develop a bad block detection program to eliminate factory bad blocks,reduce testing time,and reduce testing costs.Complete NAND Flash contact testing,functional testing,and main AC/DC parameter testing program design based on testing requirements and testing plans.This article designs a testing scheme for 3D NAND Flash based on ATE,measures and compensates for transmission line delay time in high-speed DIB board design,completes the generation of NAND Flash testing graphics and the design of vector simulation controller,and develops a functional testing and main AC/DC parameter testing program for 3D NAND Flash.This article selects a 3D NAND Flash for testing practice,analyzes the test results,and verifies the feasibility of the testing program developed in this article.
Keywords/Search Tags:NAND Flash test, test algorithms, delay compensation, test vector generation
PDF Full Text Request
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