The Study Of Error-Controllable Double-Precision Floating-Point Arithmetic Accelerator Based On FPGA

There are two types of data formats for computers,fixed-point and floating-point numbers.Under the same word length,floating-point numbers have higher precision and can represent a wider range of values.Therefore,they are widely used in processing numerical,textual,and graphical information.Floating-point operations are fundamental operations in the field of high-performance computing(HPC).With the background of big data and cloud computing,the amount of data that high-performance computing platforms need to process is increasing day by day.The researches on accelerators for floating-point operations have received much attention in the field of information technology.How to improve the performance of floating-point operations has always been a hot topic in the scientific research and engineering fields.At the same time,rounding errors of floating-point numbers can accumulate in large-scale and long-time operations,leading to unreliable or even completely incorrect calculation results.In safety-critical domains such as aerospace,military,and medical industries,unreliable calculation results may cause irreparable damage.Therefore,in the design of floating-point operation accelerators,it is necessary to improve the operation speed,it is also essential to consider the operation accuracy and reliability comprehensively.In this paper,based on the FPGA characterized by programmability and strong flexibility,a floating-point polynomial accelerator for complex single-term operations is introduced.To further solve the problem of accumulating rounding errors in large-scale and long-time floating-point operations,this paper proposes an error-controllable floating-point operation unit based on the IEEE-754 floating-point number encoding,the rounding error of floating-point numbers and related theories,as well as error-free transformation strategies.We also realize the control and compensation of rounding errors in the floating-point calculation process.Finally,the accelerator proposed in this paper is experimentally verified by a CPU-FPGA heterogeneous system.The experimental results show that in numerical relativistic simulation experiments under unrestricted symmetry,the present accelerator can obtain 53.6 higher percentage of accurate results and lower relative errors than the Intel I7 6700 K CPU under the condition of achieving 50.45 times acceleration,with higher reliability,which is more valuable for applications in computational scenarios requiring high reliability.