Design And FPGA Implementation Of LDPC Code High Speed Decoder For Leo Satellite Communication

In low-Earth orbit satellite communications,low density parity check（LDPC）codes have attracted widespread attention due to their low error leveling,high coding gain,and excellent decoding performance approaching the Shannon limit.Under the condition of ensuring that the decoding performance is not lost,using limited hardware resources to improve the throughput rate of the LDPC decoder has always been the direction that the LDPC code is applied to the actual system to achieve.Aiming at the LDPC code pattern of low earth orbit satellite communication under the Consultative Committee for Space Data Systems（CCSDS）standard,this paper designs and implements a high-throughput decoder of this code pattern on the field programmable gate array（FPGA）platform.First of all,according to the technical requirements of the volume,power consump-tion,external data interaction interface,decoding rate and bit error rate specified in the technical agreement,the hardware circuit of the high-speed decoder is designed.Taking FPGA as the main control chip and adopt the form of board design.The PCI Express in-terface circuit,DDR3 interface circuit and peripheral circuits that assist the normal opera-tion of the FPGA chip are designed in detail.Then,according to the internal high-speed data transmission architecture of the de-coding board,the PCI Express interface control logic and the DDR3 interface control logic are designed based on the FPGA platform.The PCI Express interface control logic adopts the direct memory access（DMA）mode and is designed based on the PCI Express hard core IP,realizing the high-speed data interaction between the decoding board and the PC.The DDR3 interface control logic is based on memory interface generator（MIG）IP,sup-plemented by a data management module to divide the DDR3 storage space,and realizes multi-channel data reading and writing of DDR3.Last,the commonly used LDPC decoding algorithms and decoding architecture are studied,and various decoding algorithms are simulated and analyzed based on MATLAB.According to the requirements of the technical agreement,the system uses the NMS algo-rithm with a correction factor of 0.75 and an iteration number of 10 as the decoding algo-rithm.For the decoding architecture,the system uses a partial parallel decoding architec-ture design,combining the sub-block number division method and the sub-block dimen-sion division method,a partial parallel decoding architecture with 112 variable node par-allelism and 14 check node parallelism is designed.Based on the analysis of decoding al-gorithm and decoding architecture,the LDPC decoding logic is designed.Finally,verifing the decoder board.Under the additive white gaussian noise（AWGN）channel condition of the signal-to-noise ratio_bE/N₀（28）6d B,a high-speed decoder with a decoding throughput of 1232Mbps was realized based on the Xilinx XC7K325T FPGA platform.After 24 hours of testing,no bit errors were found.