Design And Research Of 5G Communication IQ Data Compression ASIC Based On CPRI Protocol

With the rapid development of 5G,distributed base stations,which played a significant role in 4G,will continue to play its role in 5G.Especially the link based on CPRI protocol has high transmission rate and flexible networking mode,at the same time,it ensures the reliability of data transmission and the extensibility of the protocol itself,which is widely favored by various manufacturers.This paper studies the key modules of 5G fronthaul based on CPRI protocol,in the context of the rapid development of 5G,the fronthaul has always been an important research topic for various manufacturers.In order to solve the problem of large amount of data transmission between REC and RE in the fronthaul and the consumption of optical fiber resources,this paper presents a lossy I/Q data compression to reduce the throughput of fiber optic links.The design describes the AAU top layer and its key submodules in detail based on the CPRI protocol,and divides the whole design process into three stages.The first stage,design the compression module and decompression module.In this stage,the feasibility of the data compression scheme was simulated by MATLAB firstly,and the time-domain waveform,power spectrum of the data after compression and decompression were compared with the original data.Then the errors caused by compression and decompression are analyzed.Finally,the verification is carried out on the FPGA chip.The simulation results show that the compression scheme can achieve2:1 lossy compression,and the EVM caused by compression decompression is 0.58%,which effectively reduces the data throughput.The second stage,design the AAU overall design scheme.In this phase,the overall architecture of the AAU system is first defined,and divided the system into two parts: PS and PL.Then the design scheme of each sub-module is proposed,and the function of each sub-module is expounded in detail.In the third stage,based on the CPRI IP core provided by Xilinx Company,the SOC FPGA implementation of the CPRI interface and its key sub-modules,Ethernet module,I/Q data module,and vendor characteristic information module was carried out.Finally,the top layer of AAU was implemented and the test platform was built to test the whole system.The log information generated by the system test shows that the CPRI data link can be established normally.After the introduction of the compression module and decompression module the whole design consumed more logical resources,but it achieves 2:1 lossy compression and the fiber resource is greatly saved.And the design can be upgraded to support more light ports to expand the overall communication capacity and enhance the CPRI transmission rate.