Coherent Receiver Circuit Design And Key DSP Algorithm Design Implementation For Space Optical Communication System

Space optical communication has attracted the attention and favor of researchers due to its large capacity,high transmission rate,strong confidentiality and anti-interference characteristics.Coherent optical communication,due to its high sensitivity,long relay distance,large capacity,and support for multiple modulation methods,has gradually become one of the future development directions of space optical communication.At the receiving end of a coherent optical communication system,the signal after coherent detection still needs to be compensated for any damage in the signal through digital signal processing(DSP)technology.Designing and implementing real-time and parallel DSP algorithms has always been a hot and difficult research topic,and at the same time,the design and implementation of hardware receiving systems that support DSP algorithm research is particularly urgent and important.This article focuses on l0GBaud spatial coherent optical communication,researching and designing hardware receiving circuit systems,and conducting research on parallel IQ imbalance compensation algorithms and parallel carrier frequency offset estimation algorithms under 16QAM modulation format.The main research content is as follows:(1)Complete the receiver circuit design of 10GBaud-16QAM spatial coherent optical communication system.This includes the functional design,module division,chip research and selection of the receiving circuit system.(2)Based on an FPGA(Field Programmable Gate Array)chip,a IQ imbalance compensation algorithm module for the receiving end of a 10GBaud-16QAM modulation system was designed and implemented.The designed algorithm can compensate for IQ imbalance damage in the received signal at a transmission rate of 10GBaud in FPGA with low resource consumption by parallelizing data processing and optimizing key computing steps.After functional simulation verification,the designed parallel IQ imbalance compensation algorithm can compensate for IQ imbalance damage in the received signal under the conditions of sending optical power of-1dBm,receiving optical power of-32dBm,and transmission distance of 2km.After demodulation,the BER of the system is in the range of 10-5.(3)Based on an FPGA chip,a carrier frequency offset estimation algorithm module for the receiver of a 10GBaud-16QAM modulation system was designed and implemented.The designed algorithm can estimate and compensate for frequency offset damage in the received signal in FPGA,and effectively reduce the resource usage of FPGA.Under the conditions of transmitting optical power of-1dBm,receiving optical power of-32dBm,transmission distance of 2km,and frequency offset of 1GHz,the designed parallel carrier frequency offset estimation algorithm can estimate and compensate for frequency offset damage in the received signal.After demodulation,the BER of the system is in the range of 10-5.