Design Of Multi-protocol Fast Charging Chip Based On PD 3.0

As the performance of smartphones continues to improve,the demand for battery capacity is also gradually increasing,and how to safely and quickly improve charging efficiency without losing battery life has become the key to improving the cell phone application experience.In response to this problem,cell phone manufacturers have provided fast charging solutions for their own products.The PD 3.0 fast charging protocol launched by the USB-IF Alliance based on the Type-C interface is now the most widely used fast charging protocol due to its high charging power of 100W and high security.Therefore,the study of the USB PD protocol is of great significance.This thesis provides a design solution for a Source-side ASIC chip based on PD 3.0 protocol,which is compatible with QC 3.0 fast charging protocol and supports two fast charging protocols to work independently,with the advantages of small area and low cost compared to other fast charging control chips,as follows:(1)Firstly,the process of establishing the PD 3.0 fast charging protocol and the QC 3.0 fast charging protocol is analysed in terms of the pinout of the Type-C interface,the message transmission method and the feasibility of compatibility between the two protocols.Then we describe the PD 3.0 protocol message construction and power supply negotiation process according to the protocol content and briefly describe the basic architecture of the two protocols.(2)The overall architecture of the compatible fast charging chip is divided into two major parts:the PD 3.0 core and the QC 3.0 core,with the exception of the port control and other auxiliary modules,based on the principle of mutual independence of core functions and"establish first,power first".The design of the core is divided into a device policy management layer,a policy engine layer,a protocol layer and a physical layer according to the requirements of the PD 3.0 protocol,and all the layers except the physical layer are mainly built using a finite state machine approach.The policy engine layer was built with a streamlined message type to minimise the complexity of building messages and negotiating functionality.CRC-32 checksum and unchecksum,4B/5B codec and BMC codec are completed for the physical layer,and categorical coding is used to reduce the complexity and instability of logic operations in the 4B/5B decoding process.In BMC decoding,a sliding window decoding method is used to improve the accuracy of BMC decoding by averaging and verifying the decoding threshold in the leading code area.A state machine is used for port control and power mode control of the QC 3.0 core,and a multi-power mode with external enable is given to adjust the power supply current of the protocol.(3)The completed digital part of the design was simulated at module level and system level using VCS,and the analogue and digital parts were shown to work together properly through hybrid simulation using Xa-VCS.The circuit translation work of this design,such as synthesis,DFT insertion and testing,was completed using synopsys’ IC design tools,resulting in a design with 93.7%scan chain coverage,an area of 617 × 674μm2 and a power consumption of 0.0240W.