Research And Implementation Of Simulation Technology For Heterogeneous Multi-Core Processors

To achieve the performance requirements of modern broadband wireless communication technology,the development of dedicated heterogeneous multicore DSP chips is often necessary.In the process of chip design and implementation,it is important to study the simulation techniques and design and construction of simulation systems for such chips.This paper primarily focuses on the research of simulation techniques for heterogeneous multicore processors and proposes a solution for designing and constructing a simulation system.Based on the RISC-V extended instruction set architecture,the heterogeneous multicore processor designed in this study features a vector core that supports SIMD high-precision computation.The research in this article revolves around three aspects of the simulation technique for this heterogeneous multicore processor.Firstly,the heterogeneous multicore processor involves highly complex calculations and precise numerical computations.It also requires real-time performance and data parallelism.However,general SIMD-enabled simulation tools lack flexibility and precise handling of instruction data.To address this,a decoding-tiered processing single-core simulation model is proposed in this article,which enables precise simulation of a single SIMD processing core.Secondly,to overcome the limitations of functional simulation in simulating resource and target conflicts and the low efficiency of clockaccurate simulation,a coroutine-based concurrent simulation execution method is presented.This method achieves accurate pipeline timing for read and write operations,anci instruction pipelines are scheduled based on different categories of instructions in the instruction set,enabling the processor to execute instructions in a pipelined manner.Lastly,commoncommunication in multi-core processors usually relies on specific hardware architectures,making it difficult to reuse on different heterogeneous multicore processors.Therefore,a communication model for the heterogeneous multicore processor is proposed,and simulation instances of the signal processing process are performed based on this model.The research first completes the simulation design of a single core and the construction of the pipeline structure based on the requirements.Then,according to the characteristics and requirements of registers,the corresponding inter-core communication mechanism is designed to enhance the system’s flexibility and scalability,enabling task partitioning and parallel processing in a multi-core environment.In conclusion,this article presents a simulation technique model for a heterogeneous multicore processor,which includes the simulation research of a single core,instruction pipeline execution,and communication model simulation for the heterogeneous multicore processor.Such a model can assist researchers in rapidly achieving precise instruction simulation for SIMD-enabled processors and subsequently fulfill their research requirements.It can also be applicable to the porting of other commonly used processors on host operating systems.