Implementation Of Nonbinary LDPC Code Encoding And Decoding Algorithm

With the development of communication theory and very large scale integration circuits,low-density parity-check(LDPC)codes with performance close to Shannon limit are widely used in the industry.Research in recent years has shown that for short/medium codeword length,non-binary LDPC codes have better error-correction capability than their binary counterparts.However,the implementation complexity of encoding and decoding algorithms of non-binary LDPC codes is high.Aming at low complexity and high throughput,we study the encoding and decoding algorithm and its hardware implementation.The main contents of this paper are as follows.For encoders,based on the quasi-cyclic parity check matrix,the hardware implementation of a low-complexity encoder is proposed.The multiplication of sparse matrix and vector is implemented by storing the vector in random access memory and uses the row indexes of nonzero entries of each column in sparse matrix as the write address.The shift-register-adder-accumulator circuit is used to implement the multiplication of dense core matrix and vector.The implementation of the LDPC encoder with a code rate of 1/2 on a field programmable gate array(FPGA)platform shows that compared with the traditional direct encoder,the flip-flop and look-up table resources are reduced by approximately 50%.Then,based on the the bidiagonal feature of the corresponding parity check symbol part in the parity check matrix with repeat-accumulation structure,a parallel accumulation method and corresponding parallel circuit architecture are proposed.Furthermore,slow-down and cutset retiming techniques are performed on the circuit to shorten the critical path.The implementation results on the FPGA platform show that compared with the existing architecture,the proposed architecture can reduce hardware resources by 60% with a high throughput.For decoders,based on the simplified enhanced serial generalized bit-flipping decoding algorithm(SES-GBFDA),a method of truncating the vector message of the decoder to a limited value is proposed to reduce memory requirements and computational complexity,that is,truncated SES-GBFDA algorithm,design the decoder architecture for the algorithm,and implement it on FPGA.The results show that,the throughput of the decoder can reach 90 Mbps,compared with the existing decoder,the implemented decoder reduces the consumption of look-up table and register resources by 81.9% and 79.3%,respectively,with a smaller loss in decoding performance.