Research And Design Of 14 Bit SAR ADC For Digital Power System

The analog-to-digital converter（ADC）plays a key role in connecting analog domain and digital domain,so it is widely used.Among them,successive approximation analog-to-digital converter（SAR ADC）is widely used in industrial control,electric power monitoring,digital power system and other fields due to its advantages of low power consumption and small area.In recent years,especially in the digital power system,the design of analog-to-digital converter with easy integration,high precision,medium speed and low power consumption has become one of the hot research directions in recent years.This paper aims at designing a 14 bit high precision successive approximation analog-to-digital converter for digital power system.Firstly,the research background and current situation of SAR ADC at home and abroad,as well as common architectures are analyzed.Then,the key points to achieve the target are analyzed from the difficulty of designing a 14 bit analog-to-digital converter.Finally,the top architecture of the successive approximation analog-to-digital converter designed in this paper is determined and an efficient digital calibration algorithm for capacitor mismatch,misalignment error and gain error is proposed.The segmented capacitive digital-to-analog converter（DAC）with redundant structure is adopted,and the area of DAC is reduced and the actual weights of capacitors are calculated with digital calibration algorithm.The sampling switch circuit is designed to reduce the nonlinearity of the input signal and improve the stray free dynamic range.A high speed and high precision comparator is designed.The structure of three-stage pre-amplifier cascade latch is adopted.The output misalignment storage technology is used to reduce the influence of misalignment voltage and optimize the noise coefficient.The synchronous timing logic circuit is designed,and the timing distribution is optimized reasonably according to the results of simulation.The results of simulation show that the proposed digital calibration algorithm can effectively improve the effective numbers of bits,signal-to-noise distortion ratio and spurious dynamic range.In this paper,the design of schematic diagram and layout are carried out under 0.18μm BCD process,the layout area is 1.2 mm×1.1 mm,and the simulation verification is carried out.Post-simulation results show that when V_aa=5 V,V_dd=1.8 V,sampling rate is 4 MS/s,the input signal is a differential sine wave signal with 0.3125 MHz and full range,the dynamic performance of the ADC designed in this paper SNDR is 83.93 d B.The effective numbers of bits（ENOB）reaches 13.65 bit,and the spurious dynamic range（SFDR）reaches 93.6 d B.