Design Of A Low Jitter Sub-sampling Phase Locked Loop For Array TDC

In infrared laser imaging technology,Read Out Integrate Circuit(ROIC)relies on a Time-toDigital Converter(TDC)to convert the detected photon time-of-flight(Time-of-Flight,TOF)to complete the quantization,the resolution and range of the TDC directly determine the accuracy of the wide dynamic range detection data and the final imaging effect,which requires the clock generation circuit of TDC to generate a clock signal with uniform phase separation,stable duty cycle and continuously adjustable frequency.In order to reduce the quantization error of TDC,the clock signal should also meet the requirements of low jitter and low phase noise.In order to meet the requirements of the array TDC for the clock generation circuit,a SubSampling Phase-locked Loop(SS-PLL)clock generation circuit is designed in this article to achieve uniform output phase separation,continuous frequency adjustable,low jitter and so on.Starting from the stability and noise suppression requirements of the SS-PLL,this article completes the SS-PLL system and noise transfer modeling,expounds the generation mechanism of reference spurs.Through the comparative analysis with the traditional charge pump phase-locked loop,the origin of the low jitter advantage of SS-PLL is clarified.The SS-PLL circuit proposed in this article uses an auxiliary sampling loop to improve the loop gain and reduce the loop phase noise,and uses a dual-loop fourstage voltage-controlled oscillator(VCO)structure to obtain full swing output and reduce VCO high frequency noise.Sub-Sampling Phase Detector(SS-PD)and Sub-Sampling Charge Pump(SS-CP)adopt Dummy structure and add unity gain buffer to reduce the impact of non-ideal effects in SSPD/SS-CP.Under the condition of the output clock frequency of 300 MHz,the dead time of the frequency and phase detector in the auxiliary frequency lock loop is reduced to 5ns,which greatly improves the SS-PLL power-on lock time and the relock time after interference.Based on the TSMC 0.18 μm standard CMOS process,this article uses the Cadence tool to design the circuit and layout of the SS-PLL.On this basis,complete the pre-and post-simulation verification of key sub-modules and systems.The post-simulation results show that when the input reference clock is 20 MHz,the SS-PLL functions normally and can output a 200～500MHz continuous frequency adjustable clock signal.The duty cycle of the output signal is maintained at(50±2)% under each frequency and process condition,the phase deviation between adjacent phases of the eight-phase clock is within the range of(45±1)°,the maximum peak-to-peak jitter of the clock signal at the output frequency of 300 MHz is 1.69 ps,the phase noise at 1MHz off the center frequency is-119.68 d Bc/Hz,and the average power consumption of the circuit is 9.88 m A,all performances meet the index requirements,and can meet the application requirements of array TDC.