Research And Design Of High Speed Data Acquisition And Transmission Based On FPGA

Data acquisition systems are used in radar signal reception,automotive electronics,medical imaging and many other fields.Data acquisition rate and the improvement of processor performance,radar and computer technology advances,so that the requirements of data acquisition systems in various fields are increasingly high,massive data acquisition,high-speed data cache transmission has become an inevitable trend.Therefore,the research on the design of high-speed data acquisition and transmission has important application significance.To meet the above requirements,the ADS54J60 chip is configured to implement the JESD204 B interface to complete high-speed data reception,the DDR3 SDRAM controller module is designed to complete data caching,and the PCIe bus control module is designed to complete high-speed data transmission.The main work is as follows:(1)Determine the overall design scheme and divide the whole into three parts based on function: data acquisition,data caching,and data transmission.The hardware part is determined to use FPGA as the main board of the controller and Verilog language to complete the logic programming.The interface circuit is designed according to the SPI protocol,and the ADC chip function is configured to implement the JESD204 B interface to receive the data collected by the ADC.The data format conversion is completed through the digital logic acquisition part.The digital logic cache section is designed based on the AXI bus,and the cache depth configuration is done in the data transfer section.This enables highspeed data acquisition and caching.(2)Specific implementation of the design solution.The acquisition part is completed on the basis of ADC clock and register function configuration,and the JESD204 B IP parameters are set to 8 precision 16 bit channel inputs,with each channel line rate up to3.84 Gbps.The MIG IP core combined with cache digital logic is used to form the DDR3 SDRAM controller module.The XDMA IP core is used to complete the decentralized aggregated DMA operation for PCIe3.0 hardcore modules,and the maximum bus data transfer rate can reach 8GT/s to achieve high-speed data transfer.(3)The PCIe driver is designed under Linux to transfer data from the FPGA to the onboard CPU.Qt is used to design the user interface application on the PC side to receive,display and save the data transmitted on the hardware board.(4)The hardware development board and PC-based host computer are used to build the software and hardware test and verification platform.Validation of the design for acquisition function configuration and caching function and transmission function.Test results show that the ADS54J60 chip function configuration is correctly completed to achieve the JESD204 B interface to collect data.DDR3 SDRAM cache and PCIe bus transfer are designed to be implemented.The overall functionality basically meets the requirements.