Research And Design Of High Precision SAR ADC

In recent years,China’s manufacturing industry has gradually started to move from low-end to high-end,making the domestic demand for high-end analog chips increasing.Since the start of the Sino-U.S.trade war in 2018,the domestic high-end manufacturing industry has been greatly impacted,and since most of the domestic high-end chips were imported from abroad in the past,the domestic design and production of high-end chips are relatively unfamiliar,thus slowing down the development of China’s high-end manufacturing industry.In order to get rid of the situation that China is held by the United States in the field of high-end chips,China vigorously develops the chip industry and strives to be self-reliant in the field of high-end chips.As a bridge between the real world and the digital world,the analog-to-digital converter(ADC)occupies an important position in the high-end analog chips.Due to its high design difficulty and long testing cycle,it leads to its slow update iteration.Unlike low-end ADCs for general consumer products,high-end ADCs are mainly for military fields,medical devices and precision measurement fields,so the localized replacement of high-performance ADCs is of great significance to the development of China’s high-end manufacturing industry.Among ADCs,SAR ADC benefit from a highly digital structure,are highly energy efficient for low and medium precision applications,are very friendly to advanced processes,and are less affected by the equal scale reduction of devices.However,for slightly higher precision scenarios,SAR ADC suffer from significant limitations.The noise of the comparator almost limits the accuracy of SAR ADCs to about 10 bits,and their serial quantization mode of operation limits the speed significantly to the operating frequency.Based on the traditional SAR ADC structure,this thesis first provides an indepth understanding of its working principle,including the sampling process and quantization process;then analyzes the sampling process in detail,focusing on the effects caused by its non-ideal factors,such as charge injection and clock feedthrough,sampling noise and non-linearity,sampling accuracy,etc.;after that,the flip-flop mode and array structure of the capacitor array are analyzed in detail,and different flip-flop modes and array structures analysis was carried out.The flip-flop mode and array structure are analyzed in detail,and the energy efficiency of different flip-flop modes and the errors of different array structures are discussed in depth;then the core module in SAR ADC,the comparator,is analyzed in depth,and the noise of various comparators is calculated in detail and optimized according to the calculation results,and a SAR ADC with a sampling frequency of 100 MS/s and an effective number of bits is constructed on the basis of the optimized comparator.The SAR ADC with a sampling frequency of 100MS/s and an ENOB of 12 bits is constructed on the basis of the optimized comparator and simulated at different process angles,and the results show that the design has good stability and a signal-to-noise ratio of 74 d B can be obtained at different process angles.The FOMs of this design are 177.9d B and the FOMw is 5.33 f J/conversion-step,and a high figure of merit is obtained.