Research On Compiled Code Algorithm Of Double Binary Convolutional Turbo Code And Its FPGA Implementation

Turbo codes have excellent performance close to the Shannon limit,and have be-come a hot research topic in the field of channel coding since its introduction.Double Binary Convolutional Turbo Code（DB-CTC）is developed from binary turbo code,which inherits the advantages of turbo code and has the advantages of higher coding efficiency and less significant BER flat layer compared with turbo code.It has been used in airborne communication data link system and other projects and has been selected as the channel coding scheme by IEEE802.16m and other international standards.The design and imple-mentation is one of the difficulties and key points of the decoder of DB-CTC in airborne communication data chain system.In order to reduce the complexity of DB-CTC imple-mentation in airborne communication data chain system,this thesis conducts an in-depth study on DB-CTC.The innovative work of this thesis is summarized as follows:（1）The performance improvement of the MAX-LOG-MAP algorithm of DB-CTC is investigated,and the MAX-LOG-MAP algorithm with relaxed external information is obtained by successive relaxation of the external information.This algorithm has a performance improvement of about 0.25 d B over the MAX-LOG-MAP algorithm at a BER of 10^-3with only two additional multiplications and one addition operation.In addition,the MAX-LOG-MAP algorithm with relaxed and scaled external information is obtained by combining the relaxation scheme of external information with the scaling scheme,and this algorithm has about 0.3d B performance improvement compared to the MAX-LOG-MAP algorithm at a BER of 10^-3and only adds three multiplications and one addition operation.（2）The early termination iteration of DB-CTC is investigated,and the Cross Hard Desicion Aided（CHDA）stopping criterion is proposed,inspired by the Hard Desicion Aided（HDA）stopping criterion and the Cross Entropy（CE）stopping criterion.The BER performance of DB-CTC decoding using the CHDA criterion and the no-iterative stopping criterion is made consistent;the average number of iterations required using the CHDA criterion is reduced by about 0.31 than that using the HDA criterion.Based on this,the idea of the Sign Difference Ratio（SDR）stopping criterion is further utilized to increase the threshold judgment of the CHDA criterion at low signal-to-noise ratio.The average number of iterations required for DB-CTC decoding using the CHDA criterion with the added threshold judgment is reduced by about 0.69 iterations compared to that using the HDA criterion.（3）The parallel decoding structure of DB-CTC is studied,and an FPGA implemen-tation framework of improved bidirectional parallel decoding combine with segmented parallel decoding is obtained through the study of bidirectional parallel decoding,parallel iterative decoding and segmented parallel decoding structures.When the FPGA imple-mentation of DB-CTC decoder is completed using this framework,the computation delay of data such as forward/backward branch metric and external information is about 1/2n（n is the number of segmented parallelism）of the serial decoding structure.In addition,a par-allel interleaving structure is proposed based on the characteristics of DB-CTC interleaved addresses,and the interleaving/de-interleaving delay of DB-CTC under this interleaving structure is about 1/（n+1）of the serial structure.