FPGA-based Implementation Of Duo-binary Turbo Code

Turbo code was firstly proposed in 1993. It has becomed a research spot in the field of information theory for its excellect performance towards Shannon limits. Compared with general binary Turbo code, duo-binary Turbo code has higher coding efficiency, stronger error correction capability and the advantages of small decoding delay. At present, the duo-binary Turbo code has been widely used in wireless communication system.In this paper, decoding algorithm and FPGA-based implementation of duo-binary Turbo codes have been discussed.Firstly, we introduces the encoding and decoding theory and structure of the duo-binary Turbo code, improved and simplified decoding algorithm which reduces the complexity and improves the throught. Next the influence of several key factors on the performance has been analyzed, and duo-binary Turbo on different factors has been simulation under software environment.Then in terms of hardware implementation, the decoding algorithm has been analyzed and improved according to the characteristics of duo-binary Turbo code, sliding window thought has been used in decoding implementation based on soft input soft output iterative decoding algorithm in order to reduce the resource consumption and the decoding delay, specifically involved in Enhanced-Max-Log-MAP. In the hardware design, the modular thought and two level controlled structure have been adopted, aiming at realizing the window synchronous, makes the relationship between the sub-modules simpler, easier to debug the whole decoding system. In the design and realization of each module, the hardware implementation complexity, throughput and processing time delay have been taken into account for the sake of improving the generality of module and reducing the complexity of the algorithm. Finally scheme has been validated in the actual hardware platforms, the ideal results are obtained.