Research And Design Of Key Technologies Of High-Precision Analog-to-Digital Converters

In recent years,with the rapid development of integrated circuits,the demand for data collection and processing systems has moved towards speed and precision.As an critical part of the data acquisition system,Analog-to-Digital Converter(ADC)works as the bridge between analog and digital signal.SAR ADC has prompted it as one of the most popular structure of ADC in recent years due to its simple structure and easy integration.Therefore,high application value comes with the technical research and design of high-precision SAR ADC.I.In this thesis,based on the basic conversion principles of single-ended and fully differential capacitive DAC(Digital to Analog Convertor),a high-precision fully differential capacitive DAC array is analyzed,and a resistor-capacitor hybrid DAC structure is finally determined to be applied,which reduces the number of unit capacitors of the DAC array while maintaining the binary weight,reducing the the damage of parasitic capacitance.The value of unit capacitance is determined based on process mismatch and ADC sampling noise analysis.II.By analyzing the process mismatch for capacitor array,this thesis introduces a digital foreground calibration method by sorting the capacitor cell,which is based on the statistical distribution principle of process mismatch,to reduce the effect of imbalance of high weight capacitors.The size of correction unit and the scale of algorithm is determined using MATLAB and Virtuoso for model simulation.MATLAB modeling is applied to validate the SAR ADC designed in this thesis with the introduced digital foreground correction method.1000 Monte-Carlo simulation of the model with 0.1%standard deviation of the unit capacitance mismatch shows that the Signal to Noise and Distortion Ratio(SNDR)of the model before applying this calibration method is 95.49dB.The Spurious Free Dynamic Range(SFDR)is 100.38dB and the Effective Number Of Bits(ENOB)is 15.57bits.After applying the capacitive recombination calibration method,the model’s SFDR improves by 23.7dB to 124.08dB,SNDR improves by 11.33dB to106.82dB,ENOB improves by 1.88bits to 17.45bits.Meanwhile,the differential non-linearity(DNL)range reduces from[1.4,-1]to[+0.6,-0.4],the integral non-linearity(INL)range reduces from[+7.015,-7.012]to[+0.525,-0.524],the DNL range reduces by 1.4 LSB,and the INL range reduces by 12.978 LSB.III.After considering the noise,accuracy,and speed requirements of this ADC,a high-precision low-noise comparator with four-stage preamplifier and dynamic comparator is designed.Simulations show that the mismatch standard deviation of the comparator is 3.06mVand the equivalent input noise voltage is 9.07mV.The actual noise distribution of the comparator is estimated by time-domain transient simulations,and the standard deviation of the noise distribution is 17.5mV,which meets the requirements of this design.Next,the circuit reliability is verified by pre-PVT simulation in Virtuoso using the circuit built based on 180nm process.The PVT result shows that the SNDR in the pre-simulation of this circuit structure at a sampling frequency of 1MSPS is above 108dB and the SFDR is above 117dB.The Layout is drawn based on the circuit with the total area of3850×2810mm~2,and extract parasitic parameters for post-simulation.The post-simulation PVT result shows the SNDR is above 105 dB and the SFDR is above 114 dB under all circonstances.The calibration method is verified by introducing mismatch into the post-simulation,the circuit performance is compared before and after adopting the capacitive sorting recombination correction algorithm.The SNDR increased from 88.1dB to 103.82dB and the SFDR from 93.37dB to 111.5dB at a sampling frequency of 1MSPS.The average current of each power node is measured at 5V supply voltage during certain numbers of conversion cycles,and the power consumption of the analog part of the circuit is 111.335mW.The digital circuit is synthesized in Design Compiler to consume2.679mW,and the total power consumption of the circuit is 114.014mW.The Schreier FOM is calculated to be 177.37dB.