Research On Key Technologies Of Charge Pump Phase-locked Loop Based On CMOS Process

The thesis uses 65 nm CMOS process library to design three key circuits in the phaselocked loop: phase frequency detector,charge pump and fractional frequency divider.The phase frequency detector is mainly composed of TSPC D trigger and an and gate structure,under the supply voltage of 1.8V can achieve maximum working frequency 200 MHz,the width of preventive dead zone is 180 ps,range of phase discrimination for [1.91 π,1.91 π].The power consumption of phase frequency detector is 0.13 m W.The charge pump circuit is mainly composed of two clamp operational amplifiers and mirror current source.The charge pump’s maximum operating frequency is 200 MHz under the supply voltage of 1.8V and its output port operating voltage is 0.3V～1.5V.The charge pump’s static and dynamic mismatch of charge and discharge current are 0.3% and 1.9%respectively and it has the function of fast start.The change rate of the charge pump’s charge and discharge current is lower than 5% through the negative feedback circuit.The charge pump’s charge and discharge current can be adjusted from 120 u A to 540 u A to60 u A step by step.The maximum power consumption of charge pump is 6.03 m W.The designed fractional frequency divider contains three modules of circuit,which are respectively a 16-bit wide MASH 1-1-1 Sigma-Delta modulator added to LSFR,a CML structure pre-divider,and a programmable frequency divider cascaded by a 2/3 divider based on TSPC flip-flop.The power consumption of CML predivision is 3.99 m W.The power consumption of programmable frequency divider is 0.24 m W.The designed fractional frequency divider works under a 1.8V power supply voltage.The input frequency range is 5GHz to 15.6GHz,frequency division ratio is 134-254,and the decimal input bit width is 16 bits.