Research And Design Of Low Jitter Charge Pump Phase Locked Loop Based On CMOS

With the rapid evolution of communication technology and consumer electronics,signal transmission protocols have increasingly high requirements for the accuracy and stability of clock signals.As a phase feedback control system,the phase locked-loop circuit can output high-precision clock signals.Therefore,the research and design of low jitter phase-locked loop circuits has certain significance.First of all,thesis introduces the working principle and key indicators of each module of the phase-locked loop circuit,as well as the linear model and transfer function of the phase-locked loop.Guide circuit design by establishing behavior level models.A differential input/output frequency and phase frequency detector with reset delay is designed.The latch optimizes the pulse width of the reset signal to improve the symmetry of the reset signal,reducing the impact of nonideal effects.Through simulation,the phase frequency detector has a phase detection range of(-1.978 π,1.978 π).Secondly,the noise transfer function of each module is derived,and the impact of the noise of each submodule on the output signal of the system is analyzed.Under the guidance of the noise model,a low noise ring oscillator is designed.By using a delay unit with a pseudo-differential structure,the contribution of the tail current source to the lowfrequency noise of the oscillator is eliminated.At the same time,the circuit is self-biased,which reduces the impact of the noise of the external bias circuit on the output signal of the oscillator,The phase noise of the oscillator in this design is-118.4 d Bc/Hz at a frequency offset of 1 MHz.The problem of duty ratio distortion of odd frequency divider is solved through a duty ratio adjustment circuit.Finally,the overall simulation verification of the circuit is performed using software.By fitting the phase noise of each module in MATLAB,the RMS jitter value of the output clock is 2.47 ps,which is approximately 0.12% of the clock cycle,meeting the design specifications.