Research And Design Of Fractional Phase-locked Loop Based On 40nm CMOS Process

With the rapid development of 5G mobile communications,the rapid growth of mobile data traffic and the emergence of New use cases,the industry needs a new standard that can meet the growing application requirements of users.Therefore,the development of 5G NR(New Radio)technology is proposed.5G NR radio frequency transceiver is a key device used to realize 5G communication.As one of the core modules of radio frequency transceiver,phase-locked loop(PLL)performance has an important impact on5 G communication transceiver.Fractional PLL can achieve non-integer frequency conversion between input and output by using fractional frequency divider,which has higher frequency resolution and can meet the frequency accuracy requirements of RF transceiver.Through the research and design of fractional PLL,the performance and reliability of 5G NR system can be further improved.In this thesis,based on 40 nm CMOS technology,a mixed analog-digital circuit design method is used,and finally a mixed analog-digital PLL that can perform fractional N frequency division is designed.Starting from the overall structure of charge pump PLL,this thesis introduces the basic principle of PLL and the structure and working principle of each module,and simply expounds the common indicators of PLL design.In order to improve the design efficiency,the mathematical model,phase noise model and behavior level model of charge-pump PLL are established.The main work of the thesis are as follows:1)The controllable delay unit module is added to the frequency and phase detector to eliminate the phase dead zone,and the phase difference can be identified as [-1.90π,1.90π].dummy switch is designed to reduce charge injection and clock feedthrough effect.Error amplifier is used to make the source and drain voltage of the current consistent to improve the current matching degree.Simulation shows that the current mismatch is less than 2.8%.2)In the design of VCO,the structure with effectively reduced noise sensitivity function is used,the inductor uses "8" inductor to obtain high Q value,and the switching capacitor array is used to expand the operating band and reduce the phase noise.The simulation results show that the VCO frequency range is 3.74GHz～4.40 GHz,Kvco=50MHz/V,Phase noise-119.2d Bc/Hz@1MHz.3)The pre-divider in the programmable divider uses a high-speed TSPC structure to reduce the delay of the critical path.The ∑-Δ modulator uses MASH 1-1-1 structure with20 bit input decimal width to push the quantization noise to high frequency.The supply voltage of the fractional divider is 1-1.1V,the input reference frequency is 10MHz～60MHz,the internal integrated bandwidth of the loop filter is 200 KHz,the locking time is 12 us,and the phase noise is-114.3d Bc/Hz@1MHz.