Design Of Computing-in-Memory Circuits Applied For Neural Networks

In recent years,artificial intelligence(AI)technology has experienced rapid development,and intelligent devices have become increasingly important in people’s lives and work,greatly improving work efficiency and life experience.Examples include the latest Chat GPT large language model,intelligent voice assistants,wearable devices,and self-driving technology.The algorithms of these intelligent devices often require the collection of massive amounts of data,resulting in explosive growth in computation.This imposes higher demands on chip performance,and the "memory wall" problem inherent in von Neumann architecture-based computers limits the improvement of chip computing capabilities.As a new technology that promises to solve this problem,Computing-in-Memory(CIM)architecture endows memory with the ability to perform computational operations,allowing large-scale data operations to be performed inside the memory,which greatly reduces the number of data transfers and improves the energy efficiency of the system.This article first introduces the development history of in-memory computing circuits,followed by an explanation of the principle of conventional read and write operations in SRAM memory,and then briefly introduces binary neural networks.Some typical in-memory computing circuits are analyzed and compared,leading to the identification of key design points and evaluation metrics for in-memory computing architecture.For neural network computation acceleration,this article proposes an in-memory computing architecture based on 4T multiplexed computing units,which supports XNOR and Accumulate(XAC)operations.The main innovations include:Proposing a 4T multiplexed computing unit that supports XNOR operations,which can perform computations inside SRAM memory.Adopting a time-division multiplexing strategy for in-memory computing.Eight storage units share one computing unit in a time-division manner,greatly reducing the area consumption of the computing array and also reducing the calculation delay and the size of the result readout circuit.Adopting an alternating adder tree circuit consisting of an 11-transistor full adder and a 28-transistor full adder to reduce the calculation delay and power consumption of the computation result accumulation.To validate the proposed in-memory computing circuit,this article constructs a 32Kb(512x64)Computing-in-Memory circuit and conducts functional simulations.The simulation results show that the designed in-memory computing circuit can achieve correct read,write,and in-memory computing functions and has significant optimization and improvement in some technical indicators.Finally,a neural network is constructed,and this in-memory computing architecture is applied to accelerate the calculation of fully connected layers,verifying the completeness and correctness of the circuit’s functionality.