Method And Implementation Of Design For Testability Based On SoC

As semiconductor processes continue to evolve,integrated circuits are becoming more advanced,chips are becoming more integrated and the complexity of circuits and systems is increasing,making chip testing increasingly difficult and costly.In order to cope with this test situation,Design For Testability(DFT)was proposed and gradually formed a test situation with scan design,built-in self-test design and boundary-scan design as the core,but due to the many complex circuits such as processors,storage,communication interfaces and computing units integrated on SoCs(System On Chip)and IP(Intellectual Property),traditional testable design has become more and more difficult.Intellectual Property),the traditional testability design flow is not only inefficient,but also has many redundant processes due to the independence of various testability design methods,and cannot achieve controllability and observability of the inserted test logic parts,thus failing to obtain a high test coverage.How to optimise the testability design flow,efficiently use various testability design methods and improve test coverage has become an important issue in today’s IC design and manufacturing.In this thesis,a SoC design with 500,000 triggers is designed and implemented based on the DFT design scheme and flow of the Tessent Shell platform,combined with several testability design methods,and the inserted DFT hardware structure is simulated and verified based on vcs.This thesis focuses on the following aspects of the study:(1)Analyse the fault model of digital integrated circuits,introduce several major testability design methods,analyse the working principle of various testability design methods,and discuss the test structure based on the IEEE1687 standard to provide theoretical support for the subsequent concrete implementation of testability design in SoC design.(2)Analyse two DFT insertion flows under the Tessent Shell platform,compare the differences and advantages and disadvantages of the two insertion flows,focus on the Hierarchy Flow,and provide solutions for the implementation of DFT in SoC design.(3)Based on Hierarchy Flow,the overall planning of DFT implementation for SoC designs is carried out,the specific steps of DFT insertion are elaborated,and personalised configurations are made according to the actual project situation to complete the DFT insertion and verification of SoC designs.