Study Of Boundary-scan Technology

By summarizing some literatures about Boundary Scan Test (BST), thebackground and present conditions are first discussed in this thesis. With thedeveloping of very large-scale integrated circuit and the applying of nanometertechnology, packages of IC have become smaller and smaller. These changesbrought not only convenience in circuit design, but also difficulty. One side, alarge amount of nodes that in IC or function blocks can't be detected, and thismade circuit debug difficult than before; on the other side, as the result of packagesize reducing, more and more components are assembled on the Printed CircuitsBoards (PCBS), the reliability of interlinkage between IC chips has decreased, andthe interconnect test difficulty has increased. With more problems that could notbe resolved by probe appearance, Design-For-Testability (DFT) proposed in recentyears is an efficient way to overcome IC test difficulty. DFT technique requires theinterposal of test problem at the beginning of electronic system design, and it's atest method that can improve test ability by extra circuit. BST is a test technologythat developed based on DFT, by adding registers and TAP controller circuit, chipsfunction test or interconnect test can be executed easier. With the rapid progress inBST, IEEE 1149.1 international standard is made to prescribe the test ports andinstructions. Now, many corporations'IC chips have BST structure, supportingBST.BST structure and BST theory are second discussed in this paper, byunderstanding basal theory, bring forward the test vectors'disposal, and simplifytest vectors from test-link structure. Through theory researching, using DFT incircuit design and validate the test method.BST control system design is bring out based on BST research in thesis and thedesign emphasis is on the logic of Boundary Scan Master (BSM), which is the coredevice of this control system. By the analysis of control function, divide thesystem into several parts, using top-to-down technique, realized the logic design inVHDL.