Research Of The Key Digital Technologies In 14-bit Ultra High Speed Pipelined ADC

With the continuous evolution of integrated circuit manufacturing processes,using digital circuits to process signals has become the mainstream,and as a bridge between the analog world and the digital world,Analog to Digital Converter(ADC)has also achieved significant development.Due to its excellent sampling rate and high resolution,pipelined ADC have become the most widely used architecture nowadays.Therefore,this thesis will focus on the key digital circuit technologies applied to pipelined ADC.This thesis describes the key digital technologies applied to pipelined ADC,including digital calibration algorithms,Digital Down Converter(DDC),and JESD204 B interface protocol.Based on this,a DDC circuit for 14 bit 1.6 GSPS ADC is designed based on a 28 nm CMOS process.When designing DDC circuit,the structure of the phase accumulator was optimized,providing a more excellent solution for the fast frequency hopping application of numerically controlled oscillator(NCO),realizing the function of unlimited switching frequency and maintaining phase synchronization at all times.In order to achieve faster processing speed,this thesis optimizes the clock structure of the cascaded filter and shortens the cascade delay of the filter.At the same time,when designing the half band filter circuit structure,a polyphase decomposition structure is introduced,which saves nearly half of the delay units,while reducing the area,increasing the operation speed of the filter,further shortening the data processing delay.The 14 bit 1.6 GSPS pipeline ADC designed in this thesis has a digital layout area of 3390.48 μm×474 μm.The post simulation results show that under the condition of a sampling rate of 1.6 GHz and an input signal frequency of 15 MHz,the SFDR of the ADC is 90.26 d B,the SNDR is 75.75 d B,the ENOB is 12.29 bits,and the digital part power consumption is about 88.8 m W.